/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : wf_phyrx_ctrl.h
//[Revision time]   : Tue Apr 17 10:04:54 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __WF_PHYRX_CTRL_REGS_H__
#define __WF_PHYRX_CTRL_REGS_H__

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     WF_PHYRX_CTRL CR Definitions
//
//****************************************************************************

#define WF_PHYRX_CTRL_BASE                                     0x82000000

#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR                      (WF_PHYRX_CTRL_BASE + 0x000) // 0000
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR                 (WF_PHYRX_CTRL_BASE + 0x004) // 0004
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_MODE_ADDR            (WF_PHYRX_CTRL_BASE + 0x008) // 0008
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_ENAB_ADDR            (WF_PHYRX_CTRL_BASE + 0x00C) // 000C
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_ADDR          (WF_PHYRX_CTRL_BASE + 0x010) // 0010
#define WF_PHYRX_CTRL_CR_BAND0_OUTER_VARCK_TABLE_ADDR          (WF_PHYRX_CTRL_BASE + 0x014) // 0014
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR                   (WF_PHYRX_CTRL_BASE + 0x020) // 0020
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x0024) // 0024
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_ADDR             (WF_PHYRX_CTRL_BASE + 0x0030) // 0030
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_ADDR             (WF_PHYRX_CTRL_BASE + 0x0040) // 0040
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS1_ADDR           (WF_PHYRX_CTRL_BASE + 0x0048) // 0048
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_ADDR                       (WF_PHYRX_CTRL_BASE + 0x004C) // 004C
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_ADDR                (WF_PHYRX_CTRL_BASE + 0x0050) // 0050
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_ADDR                   (WF_PHYRX_CTRL_BASE + 0x0054) // 0054
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_ADDR                (WF_PHYRX_CTRL_BASE + 0x0068) // 0068
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR                     (WF_PHYRX_CTRL_BASE + 0x0070) // 0070
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_ADDR               (WF_PHYRX_CTRL_BASE + 0x0100) // 0100
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x0200) // 0200
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS_ADDR            (WF_PHYRX_CTRL_BASE + 0x0204) // 0204
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR                  (WF_PHYRX_CTRL_BASE + 0x0208) // 0208
#define WF_PHYRX_CTRL_RO_BAND0_MISC_IRQ_STA_ADDR               (WF_PHYRX_CTRL_BASE + 0x020C) // 020C
#define WF_PHYRX_CTRL_CR_BAND0_TRX_WDT_RST_MASK_ADDR           (WF_PHYRX_CTRL_BASE + 0x0210) // 0210
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x0214) // 0214
#define WF_PHYRX_CTRL_CR_BAND0_FFT_MANU_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x0300) // 0300
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x0304) // 0304
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_ADDR              (WF_PHYRX_CTRL_BASE + 0x0308) // 0308
#define WF_PHYRX_CTRL_RO_BAND0_FFT_CSD_DBG_ADDR                (WF_PHYRX_CTRL_BASE + 0x030C) // 030C
#define WF_PHYRX_CTRL_RO_BAND0_STAT_CORE_ADDR                  (WF_PHYRX_CTRL_BASE + 0x0310) // 0310
#define WF_PHYRX_CTRL_RO_BAND0_STAT_REQARB_ADDR                (WF_PHYRX_CTRL_BASE + 0x0314) // 0314
#define WF_PHYRX_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x0320) // 0320
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR                      (WF_PHYRX_CTRL_BASE + 0x0400) // 0400
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR                      (WF_PHYRX_CTRL_BASE + 0x0404) // 0404
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR0_MASK_ADDR                 (WF_PHYRX_CTRL_BASE + 0x0408) // 0408
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR1_MASK_ADDR                 (WF_PHYRX_CTRL_BASE + 0x040C) // 040C
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR2_MASK_ADDR                 (WF_PHYRX_CTRL_BASE + 0x0410) // 0410
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR3_MASK_ADDR                 (WF_PHYRX_CTRL_BASE + 0x0414) // 0414
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_ADDR            (WF_PHYRX_CTRL_BASE + 0x0418) // 0418
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR0_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x0428) // 0428
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR1_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x042C) // 042C
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR2_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x0430) // 0430
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR3_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x0434) // 0434
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_TRGFSM_ADDR              (WF_PHYRX_CTRL_BASE + 0x0438) // 0438
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0500) // 0500
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK0_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0504) // 0504
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK1_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0508) // 0508
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK2_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x050C) // 050C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK3_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0510) // 0510
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0514) // 0514
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_ADDR        (WF_PHYRX_CTRL_BASE + 0x0520) // 0520
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_ADDR      (WF_PHYRX_CTRL_BASE + 0x0524) // 0524
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_ADDR      (WF_PHYRX_CTRL_BASE + 0x0528) // 0528
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x0530) // 0530
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x0534) // 0534
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x0538) // 0538
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x053C) // 053C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x0540) // 0540
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x0544) // 0544
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x0548) // 0548
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x054C) // 054C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x0550) // 0550
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x0554) // 0554
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x0558) // 0558
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x055C) // 055C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_STAT_CTRL_ADDR           (WF_PHYRX_CTRL_BASE + 0x0560) // 0560
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_FUNIT_ADDR          (WF_PHYRX_CTRL_BASE + 0x0564) // 0564
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0580) // 0580
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK0_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0584) // 0584
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK1_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0588) // 0588
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK2_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x058C) // 058C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK3_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0590) // 0590
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0594) // 0594
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_ADDR        (WF_PHYRX_CTRL_BASE + 0x05A0) // 05A0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_ADDR      (WF_PHYRX_CTRL_BASE + 0x05A4) // 05A4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_ADDR      (WF_PHYRX_CTRL_BASE + 0x05A8) // 05A8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x05B0) // 05B0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x05B4) // 05B4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x05B8) // 05B8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x05BC) // 05BC
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x05C0) // 05C0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x05C4) // 05C4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x05C8) // 05C8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x05CC) // 05CC
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x05D0) // 05D0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x05D4) // 05D4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x05D8) // 05D8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x05DC) // 05DC
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_STAT_CTRL_ADDR           (WF_PHYRX_CTRL_BASE + 0x05E0) // 05E0
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_FUNIT_ADDR          (WF_PHYRX_CTRL_BASE + 0x05E4) // 05E4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0600) // 0600
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK0_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0604) // 0604
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK1_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0608) // 0608
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK2_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x060C) // 060C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK3_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0610) // 0610
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0614) // 0614
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_ADDR        (WF_PHYRX_CTRL_BASE + 0x0620) // 0620
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_ADDR      (WF_PHYRX_CTRL_BASE + 0x0624) // 0624
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_ADDR      (WF_PHYRX_CTRL_BASE + 0x0628) // 0628
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x0630) // 0630
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x0634) // 0634
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x0638) // 0638
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x063C) // 063C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x0640) // 0640
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x0644) // 0644
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x0648) // 0648
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x064C) // 064C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x0650) // 0650
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x0654) // 0654
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x0658) // 0658
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x065C) // 065C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_STAT_CTRL_ADDR           (WF_PHYRX_CTRL_BASE + 0x0660) // 0660
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_FUNIT_ADDR          (WF_PHYRX_CTRL_BASE + 0x0664) // 0664
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0680) // 0680
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK0_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0684) // 0684
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK1_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0688) // 0688
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK2_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x068C) // 068C
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK3_COMBO_ADDR         (WF_PHYRX_CTRL_BASE + 0x0690) // 0690
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_COMBO_ADDR          (WF_PHYRX_CTRL_BASE + 0x0694) // 0694
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_ADDR        (WF_PHYRX_CTRL_BASE + 0x06A0) // 06A0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_ADDR      (WF_PHYRX_CTRL_BASE + 0x06A4) // 06A4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_ADDR      (WF_PHYRX_CTRL_BASE + 0x06A8) // 06A8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x06B0) // 06B0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_CAGC_ADDR           (WF_PHYRX_CTRL_BASE + 0x06B4) // 06B4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x06B8) // 06B8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_OPOST_ADDR          (WF_PHYRX_CTRL_BASE + 0x06BC) // 06BC
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x06C0) // 06C0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_FFT_ADDR            (WF_PHYRX_CTRL_BASE + 0x06C4) // 06C4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x06C8) // 06C8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXTD_ADDR           (WF_PHYRX_CTRL_BASE + 0x06CC) // 06CC
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x06D0) // 06D0
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_AGC_ADDR            (WF_PHYRX_CTRL_BASE + 0x06D4) // 06D4
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x06D8) // 06D8
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXFE_ADDR           (WF_PHYRX_CTRL_BASE + 0x06DC) // 06DC
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_STAT_CTRL_ADDR           (WF_PHYRX_CTRL_BASE + 0x06E0) // 06E0
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_FUNIT_ADDR          (WF_PHYRX_CTRL_BASE + 0x06E4) // 06E4
#define WF_PHYRX_CTRL_CR_DBGCNT1_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0700) // 0700
#define WF_PHYRX_CTRL_CR_DBGCNT2_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0704) // 0704
#define WF_PHYRX_CTRL_CR_DBGCNT3_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0708) // 0708
#define WF_PHYRX_CTRL_RO_DBGCNT1_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0710) // 0710
#define WF_PHYRX_CTRL_RO_DBGCNT2_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0714) // 0714
#define WF_PHYRX_CTRL_RO_DBGCNT3_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0718) // 0718
#define WF_PHYRX_CTRL_RO_DBGCNT4_ADDR                          (WF_PHYRX_CTRL_BASE + 0x071C) // 071C
#define WF_PHYRX_CTRL_RO_DBGCNT5_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0720) // 0720
#define WF_PHYRX_CTRL_RO_DBGCNT6_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0724) // 0724
#define WF_PHYRX_CTRL_RO_DBGCNT7_ADDR                          (WF_PHYRX_CTRL_BASE + 0x0728) // 0728
#define WF_PHYRX_CTRL_RO_DBGCNT8_ADDR                          (WF_PHYRX_CTRL_BASE + 0x072C) // 072C
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0800) // 0800
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0804) // 0804
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0808) // 0808
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR                        (WF_PHYRX_CTRL_BASE + 0x080C) // 080C
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0810) // 0810
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0814) // 0814
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0818) // 0818
#define WF_PHYRX_CTRL_CR_RDD_TOP_7_ADDR                        (WF_PHYRX_CTRL_BASE + 0x081C) // 081C
#define WF_PHYRX_CTRL_CR_RDD_TOP_8_ADDR                        (WF_PHYRX_CTRL_BASE + 0x0820) // 0820
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR                       (WF_PHYRX_CTRL_BASE + 0x0830) // 0830
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_ADDR                       (WF_PHYRX_CTRL_BASE + 0x0834) // 0834
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_ADDR                       (WF_PHYRX_CTRL_BASE + 0x0838) // 0838
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_ADDR                       (WF_PHYRX_CTRL_BASE + 0x083C) // 083C
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_ADDR                       (WF_PHYRX_CTRL_BASE + 0x0840) // 0840
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR                       (WF_PHYRX_CTRL_BASE + 0x0844) // 0844
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1000) // 1000
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1004) // 1004
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1008) // 1008
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_ADDR                 (WF_PHYRX_CTRL_BASE + 0x100C) // 100C
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS0_ADDR               (WF_PHYRX_CTRL_BASE + 0x1010) // 1010
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS1_ADDR               (WF_PHYRX_CTRL_BASE + 0x1014) // 1014
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS2_ADDR               (WF_PHYRX_CTRL_BASE + 0x1018) // 1018
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS3_ADDR               (WF_PHYRX_CTRL_BASE + 0x101C) // 101C
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS4_ADDR               (WF_PHYRX_CTRL_BASE + 0x1020) // 1020
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS5_ADDR               (WF_PHYRX_CTRL_BASE + 0x1024) // 1024
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS6_ADDR               (WF_PHYRX_CTRL_BASE + 0x1028) // 1028
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS7_ADDR               (WF_PHYRX_CTRL_BASE + 0x102C) // 102C
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS8_ADDR               (WF_PHYRX_CTRL_BASE + 0x1030) // 1030
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS9_ADDR               (WF_PHYRX_CTRL_BASE + 0x1034) // 1034
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_MU_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1038) // 1038
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_FSM_ADDR                (WF_PHYRX_CTRL_BASE + 0x103C) // 103C
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x1040) // 1040
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x1044) // 1044
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_ADDR          (WF_PHYRX_CTRL_BASE + 0x1048) // 1048
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR          (WF_PHYRX_CTRL_BASE + 0x104C) // 104C
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_ADDR             (WF_PHYRX_CTRL_BASE + 0x1050) // 1050
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x1054) // 1054
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x1058) // 1058
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x105C) // 105C
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x1060) // 1060
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_2_ADDR              (WF_PHYRX_CTRL_BASE + 0x1064) // 1064
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_3_ADDR              (WF_PHYRX_CTRL_BASE + 0x1068) // 1068
#define WF_PHYRX_CTRL_RO_BAND0_GIDTAB_STATUS_ADDR              (WF_PHYRX_CTRL_BASE + 0x106C) // 106C
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x1080) // 1080
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR               (WF_PHYRX_CTRL_BASE + 0x1090) // 1090
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_ADDR                (WF_PHYRX_CTRL_BASE + 0x1094) // 1094
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_ADDR              (WF_PHYRX_CTRL_BASE + 0x1098) // 1098
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_ADDR                (WF_PHYRX_CTRL_BASE + 0x109C) // 109C
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_ADDR            (WF_PHYRX_CTRL_BASE + 0x10A0) // 10A0
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x10B0) // 10B0
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x10B4) // 10B4
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR                 (WF_PHYRX_CTRL_BASE + 0x10B8) // 10B8
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR                 (WF_PHYRX_CTRL_BASE + 0x10BC) // 10BC
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER5_ADDR                 (WF_PHYRX_CTRL_BASE + 0x10C0) // 10C0
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER6_ADDR                 (WF_PHYRX_CTRL_BASE + 0x10C4) // 10C4
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_ADDR           (WF_PHYRX_CTRL_BASE + 0x10D0) // 10D0
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR                  (WF_PHYRX_CTRL_BASE + 0x1100) // 1100
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x1104) // 1104
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ER_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x1108) // 1108
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x110C) // 110C
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_ADDR              (WF_PHYRX_CTRL_BASE + 0x1110) // 1110
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_ADDR              (WF_PHYRX_CTRL_BASE + 0x1114) // 1114
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_ADDR              (WF_PHYRX_CTRL_BASE + 0x1118) // 1118
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_ADDR          (WF_PHYRX_CTRL_BASE + 0x111C) // 111C
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_ADDR          (WF_PHYRX_CTRL_BASE + 0x1120) // 1120
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE3_ADDR          (WF_PHYRX_CTRL_BASE + 0x1124) // 1124
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_SU_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x1128) // 1128
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_ER_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x112C) // 112C
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_MU_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x1130) // 1130
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_TB_CHK_ADDR               (WF_PHYRX_CTRL_BASE + 0x1134) // 1134
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_NDP_CHK_ADDR              (WF_PHYRX_CTRL_BASE + 0x1138) // 1138
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_PFD_ADDR                  (WF_PHYRX_CTRL_BASE + 0x113C) // 113C
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR                   (WF_PHYRX_CTRL_BASE + 0x1140) // 1140
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR                  (WF_PHYRX_CTRL_BASE + 0x1144) // 1144
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR             (WF_PHYRX_CTRL_BASE + 0x1148) // 1148
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_ADDR                 (WF_PHYRX_CTRL_BASE + 0x114C) // 114C
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1150) // 1150
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1154) // 1154
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR                 (WF_PHYRX_CTRL_BASE + 0x1158) // 1158
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR                 (WF_PHYRX_CTRL_BASE + 0x115C) // 115C
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_ADDR              (WF_PHYRX_CTRL_BASE + 0x1160) // 1160
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS1_ADDR             (WF_PHYRX_CTRL_BASE + 0x1170) // 1170
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS2_ADDR             (WF_PHYRX_CTRL_BASE + 0x1174) // 1174
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS3_ADDR             (WF_PHYRX_CTRL_BASE + 0x1178) // 1178
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS4_ADDR             (WF_PHYRX_CTRL_BASE + 0x117C) // 117C
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS5_ADDR             (WF_PHYRX_CTRL_BASE + 0x1180) // 1180
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS6_ADDR             (WF_PHYRX_CTRL_BASE + 0x1184) // 1184
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS7_ADDR             (WF_PHYRX_CTRL_BASE + 0x1188) // 1188
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS8_ADDR             (WF_PHYRX_CTRL_BASE + 0x118C) // 118C
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS9_ADDR             (WF_PHYRX_CTRL_BASE + 0x1190) // 1190
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS10_ADDR            (WF_PHYRX_CTRL_BASE + 0x1194) // 1194
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS11_ADDR            (WF_PHYRX_CTRL_BASE + 0x1198) // 1198
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR               (WF_PHYRX_CTRL_BASE + 0x11A0) // 11A0
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_ADDR             (WF_PHYRX_CTRL_BASE + 0x11A8) // 11A8
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL2_ADDR             (WF_PHYRX_CTRL_BASE + 0x11AC) // 11AC
#define WF_PHYRX_CTRL_RO_BAND0_LG_SIG_ADDR                     (WF_PHYRX_CTRL_BASE + 0x11B0) // 11B0
#define WF_PHYRX_CTRL_RO_BAND0_RL_SIG_ADDR                     (WF_PHYRX_CTRL_BASE + 0x11B4) // 11B4
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A1_ADDR                  (WF_PHYRX_CTRL_BASE + 0x11B8) // 11B8
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A2_ADDR                  (WF_PHYRX_CTRL_BASE + 0x11BC) // 11BC
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_ADDR          (WF_PHYRX_CTRL_BASE + 0x1900) // 1900
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_ADDR          (WF_PHYRX_CTRL_BASE + 0x1904) // 1904
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_2_ADDR          (WF_PHYRX_CTRL_BASE + 0x1910) // 1910
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_3_ADDR          (WF_PHYRX_CTRL_BASE + 0x1914) // 1914
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_4_ADDR          (WF_PHYRX_CTRL_BASE + 0x1918) // 1918
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_5_ADDR          (WF_PHYRX_CTRL_BASE + 0x191C) // 191C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_TEST_MODE_0_ADDR     (WF_PHYRX_CTRL_BASE + 0x1920) // 1920
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_ADDR   (WF_PHYRX_CTRL_BASE + 0x1928) // 1928
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR                  (WF_PHYRX_CTRL_BASE + 0x19B0) // 19B0
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_ADDR                  (WF_PHYRX_CTRL_BASE + 0x19B4) // 19B4
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_ADDR                  (WF_PHYRX_CTRL_BASE + 0x19B8) // 19B8
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_ADDR                   (WF_PHYRX_CTRL_BASE + 0x19BC) // 19BC
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_ADDR    (WF_PHYRX_CTRL_BASE + 0x19C0) // 19C0
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_1_ADDR    (WF_PHYRX_CTRL_BASE + 0x19C4) // 19C4
#define WF_PHYRX_CTRL_RO_BAND0_RXV_0_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19D0) // 19D0
#define WF_PHYRX_CTRL_RO_BAND0_RXV_1_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19D4) // 19D4
#define WF_PHYRX_CTRL_RO_BAND0_RXV_2_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19D8) // 19D8
#define WF_PHYRX_CTRL_RO_BAND0_RXV_3_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19DC) // 19DC
#define WF_PHYRX_CTRL_RO_BAND0_RXV_4_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19E0) // 19E0
#define WF_PHYRX_CTRL_RO_BAND0_RXV_5_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19E4) // 19E4
#define WF_PHYRX_CTRL_RO_BAND0_RXV_6_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19E8) // 19E8
#define WF_PHYRX_CTRL_RO_BAND0_RXV_7_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19EC) // 19EC
#define WF_PHYRX_CTRL_RO_BAND0_RXV_8_ADDR                      (WF_PHYRX_CTRL_BASE + 0x19F0) // 19F0
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_ADDR                  (WF_PHYRX_CTRL_BASE + 0x19F4) // 19F4
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_44_ADDR                  (WF_PHYRX_CTRL_BASE + 0x19F8) // 19F8
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD0_ADDR               (WF_PHYRX_CTRL_BASE + 0x1A00) // 1A00
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD1_ADDR               (WF_PHYRX_CTRL_BASE + 0x1A04) // 1A04
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_ADDR (WF_PHYRX_CTRL_BASE + 0x1A08) // 1A08
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A0C) // 1A0C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A10) // 1A10
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A14) // 1A14
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A18) // 1A18
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A1C) // 1A1C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A20) // 1A20
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A24) // 1A24
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A28) // 1A28
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A2C) // 1A2C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MASK_ADDR       (WF_PHYRX_CTRL_BASE + 0x1A30) // 1A30
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_PAT_ADDR        (WF_PHYRX_CTRL_BASE + 0x1A34) // 1A34
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_CNT_ADDR        (WF_PHYRX_CTRL_BASE + 0x1A38) // 1A38
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A3C) // 1A3C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A40) // 1A40
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A44) // 1A44
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A48) // 1A48
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A4C) // 1A4C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A50) // 1A50
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A54) // 1A54
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A58) // 1A58
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A5C) // 1A5C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MASK_ADDR       (WF_PHYRX_CTRL_BASE + 0x1A60) // 1A60
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_PAT_ADDR        (WF_PHYRX_CTRL_BASE + 0x1A64) // 1A64
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_CNT_ADDR        (WF_PHYRX_CTRL_BASE + 0x1A68) // 1A68
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A6C) // 1A6C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A70) // 1A70
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A74) // 1A74
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A78) // 1A78
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A7C) // 1A7C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A80) // 1A80
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A84) // 1A84
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A88) // 1A88
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_ADDR   (WF_PHYRX_CTRL_BASE + 0x1A8C) // 1A8C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MASK_ADDR       (WF_PHYRX_CTRL_BASE + 0x1A90) // 1A90
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_PAT_ADDR        (WF_PHYRX_CTRL_BASE + 0x1A94) // 1A94
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_CNT_ADDR        (WF_PHYRX_CTRL_BASE + 0x1A98) // 1A98
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_ADDR  (WF_PHYRX_CTRL_BASE + 0x1A9C) // 1A9C
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AA0) // 1AA0
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AA4) // 1AA4
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AA8) // 1AA8
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AAC) // 1AAC
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AB0) // 1AB0
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AB4) // 1AB4
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_ADDR  (WF_PHYRX_CTRL_BASE + 0x1AB8) // 1AB8
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_ADDR        (WF_PHYRX_CTRL_BASE + 0x1ABC) // 1ABC
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_ADDR (WF_PHYRX_CTRL_BASE + 0x1B00) // 1B00
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_ADDR (WF_PHYRX_CTRL_BASE + 0x1B04) // 1B04
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_ADDR  (WF_PHYRX_CTRL_BASE + 0x1B08) // 1B08
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_ADDR (WF_PHYRX_CTRL_BASE + 0x1B0C) // 1B0C
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_ADDR (WF_PHYRX_CTRL_BASE + 0x1B10) // 1B10
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_ADDR (WF_PHYRX_CTRL_BASE + 0x1B14) // 1B14
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_ADDR (WF_PHYRX_CTRL_BASE + 0x1B18) // 1B18
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_ADDR (WF_PHYRX_CTRL_BASE + 0x1B1C) // 1B1C
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_ADDR (WF_PHYRX_CTRL_BASE + 0x1B20) // 1B20
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_ADDR  (WF_PHYRX_CTRL_BASE + 0x1B24) // 1B24
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_ADDR (WF_PHYRX_CTRL_BASE + 0x1B28) // 1B28
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_ADDR (WF_PHYRX_CTRL_BASE + 0x1B2C) // 1B2C
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_ADDR (WF_PHYRX_CTRL_BASE + 0x1B30) // 1B30
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_ADDR (WF_PHYRX_CTRL_BASE + 0x1B34) // 1B34
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_BBUID_ADDR           (WF_PHYRX_CTRL_BASE + 0x1B38) // 1B38
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_0_ADDR     (WF_PHYRX_CTRL_BASE + 0x1B3C) // 1B3C
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_1_ADDR     (WF_PHYRX_CTRL_BASE + 0x1B40) // 1B40
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_0_ADDR          (WF_PHYRX_CTRL_BASE + 0x1B44) // 1B44
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_1_ADDR          (WF_PHYRX_CTRL_BASE + 0x1B48) // 1B48
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PIPE_ADDR            (WF_PHYRX_CTRL_BASE + 0x1B4C) // 1B4C
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_MODE_ADDR            (WF_PHYRX_CTRL_BASE + 0x2000) // 2000
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_ENAB_ADDR            (WF_PHYRX_CTRL_BASE + 0x2004) // 2004
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_ADDR          (WF_PHYRX_CTRL_BASE + 0x2010) // 2010
#define WF_PHYRX_CTRL_CR_BAND1_OUTER_VARCK_TABLE_ADDR          (WF_PHYRX_CTRL_BASE + 0x2014) // 2014
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR                   (WF_PHYRX_CTRL_BASE + 0x2020) // 2020
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR               (WF_PHYRX_CTRL_BASE + 0x2024) // 2024
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_ADDR                (WF_PHYRX_CTRL_BASE + 0x2030) // 2030
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x220C) // 220C
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS0_ADDR           (WF_PHYRX_CTRL_BASE + 0x2210) // 2210
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS1_ADDR           (WF_PHYRX_CTRL_BASE + 0x2214) // 2214
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_RST_MASK_ADDR           (WF_PHYRX_CTRL_BASE + 0x2218) // 2218
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x221C) // 221C
#define WF_PHYRX_CTRL_RO_BAND1_MISC_IRQ_STA_ADDR               (WF_PHYRX_CTRL_BASE + 0x2220) // 2220
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_ADDR             (WF_PHYRX_CTRL_BASE + 0x2230) // 2230
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR                  (WF_PHYRX_CTRL_BASE + 0x2248) // 2248
#define WF_PHYRX_CTRL_CR_BAND1_FFT_MANU_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x2300) // 2300
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x2304) // 2304
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_ADDR              (WF_PHYRX_CTRL_BASE + 0x2308) // 2308
#define WF_PHYRX_CTRL_RO_BAND1_FFT_CSD_DBG_ADDR                (WF_PHYRX_CTRL_BASE + 0x230C) // 230C
#define WF_PHYRX_CTRL_RO_BAND1_STAT_CORE_ADDR                  (WF_PHYRX_CTRL_BASE + 0x2310) // 2310
#define WF_PHYRX_CTRL_RO_BAND1_STAT_REQARB_ADDR                (WF_PHYRX_CTRL_BASE + 0x2314) // 2314
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR0_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x2428) // 2428
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR1_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x242C) // 242C
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR2_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x2430) // 2430
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR3_TRIG_ADDR           (WF_PHYRX_CTRL_BASE + 0x2434) // 2434
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_TRGFSM_ADDR              (WF_PHYRX_CTRL_BASE + 0x2438) // 2438
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK3_ADDR             (WF_PHYRX_CTRL_BASE + 0x2490) // 2490
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT1_STAT_ADDR              (WF_PHYRX_CTRL_BASE + 0x2494) // 2494
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_ADDR               (WF_PHYRX_CTRL_BASE + 0x2500) // 2500
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK0_ADDR              (WF_PHYRX_CTRL_BASE + 0x2504) // 2504
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK1_ADDR              (WF_PHYRX_CTRL_BASE + 0x2508) // 2508
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK2_ADDR              (WF_PHYRX_CTRL_BASE + 0x250C) // 250C
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK3_ADDR              (WF_PHYRX_CTRL_BASE + 0x2510) // 2510
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT_STAT_ADDR               (WF_PHYRX_CTRL_BASE + 0x2514) // 2514
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_ADDR              (WF_PHYRX_CTRL_BASE + 0x2580) // 2580
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK0_ADDR             (WF_PHYRX_CTRL_BASE + 0x2584) // 2584
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK1_ADDR             (WF_PHYRX_CTRL_BASE + 0x2588) // 2588
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK2_ADDR             (WF_PHYRX_CTRL_BASE + 0x258C) // 258C
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C00) // 2C00
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C04) // 2C04
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C08) // 2C08
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C0C) // 2C0C
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C10) // 2C10
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C14) // 2C14
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C18) // 2C18
#define WF_PHYRX_CTRL_CR_RDD1_TOP_7_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C1C) // 2C1C
#define WF_PHYRX_CTRL_CR_RDD1_TOP_8_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C20) // 2C20
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C30) // 2C30
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C34) // 2C34
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C38) // 2C38
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C3C) // 2C3C
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C40) // 2C40
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C44) // 2C44
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C50) // 2C50
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C54) // 2C54
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C58) // 2C58
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C5C) // 2C5C
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C60) // 2C60
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C64) // 2C64
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C68) // 2C68
#define WF_PHYRX_CTRL_CR_RDD2_TOP_7_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C6C) // 2C6C
#define WF_PHYRX_CTRL_CR_RDD2_TOP_8_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2C70) // 2C70
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C80) // 2C80
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C84) // 2C84
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C88) // 2C88
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C8C) // 2C8C
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C90) // 2C90
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2C94) // 2C94
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CA0) // 2CA0
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CA4) // 2CA4
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CA8) // 2CA8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CAC) // 2CAC
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CB0) // 2CB0
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CB4) // 2CB4
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CB8) // 2CB8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_7_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CBC) // 2CBC
#define WF_PHYRX_CTRL_CR_RDD3_TOP_8_ADDR                       (WF_PHYRX_CTRL_BASE + 0x2CC0) // 2CC0
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2CC4) // 2CC4
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2CC8) // 2CC8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2CCC) // 2CCC
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2CD0) // 2CD0
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2CD4) // 2CD4
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_ADDR                      (WF_PHYRX_CTRL_BASE + 0x2CD8) // 2CD8
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR                 (WF_PHYRX_CTRL_BASE + 0x3000) // 3000
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x3004) // 3004
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x3008) // 3008
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS0_ADDR               (WF_PHYRX_CTRL_BASE + 0x3010) // 3010
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS1_ADDR               (WF_PHYRX_CTRL_BASE + 0x3014) // 3014
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS2_ADDR               (WF_PHYRX_CTRL_BASE + 0x3018) // 3018
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS3_ADDR               (WF_PHYRX_CTRL_BASE + 0x301C) // 301C
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS4_ADDR               (WF_PHYRX_CTRL_BASE + 0x3020) // 3020
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS5_ADDR               (WF_PHYRX_CTRL_BASE + 0x3024) // 3024
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS6_ADDR               (WF_PHYRX_CTRL_BASE + 0x3028) // 3028
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS7_ADDR               (WF_PHYRX_CTRL_BASE + 0x302C) // 302C
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS8_ADDR               (WF_PHYRX_CTRL_BASE + 0x3030) // 3030
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS9_ADDR               (WF_PHYRX_CTRL_BASE + 0x3034) // 3034
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_MU_ADDR             (WF_PHYRX_CTRL_BASE + 0x3038) // 3038
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_FSM_ADDR            (WF_PHYRX_CTRL_BASE + 0x303C) // 303C
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x3040) // 3040
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x3044) // 3044
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_ADDR          (WF_PHYRX_CTRL_BASE + 0x3048) // 3048
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR          (WF_PHYRX_CTRL_BASE + 0x304C) // 304C
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_ADDR             (WF_PHYRX_CTRL_BASE + 0x3050) // 3050
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x3054) // 3054
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x3058) // 3058
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x305C) // 305C
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x3060) // 3060
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_2_ADDR              (WF_PHYRX_CTRL_BASE + 0x3064) // 3064
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_3_ADDR              (WF_PHYRX_CTRL_BASE + 0x3068) // 3068
#define WF_PHYRX_CTRL_RO_BAND1_GIDTAB_STATUS_ADDR              (WF_PHYRX_CTRL_BASE + 0x306C) // 306C
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR            (WF_PHYRX_CTRL_BASE + 0x3080) // 3080
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR               (WF_PHYRX_CTRL_BASE + 0x3090) // 3090
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_ADDR                (WF_PHYRX_CTRL_BASE + 0x3094) // 3094
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_ADDR              (WF_PHYRX_CTRL_BASE + 0x3098) // 3098
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_ADDR                (WF_PHYRX_CTRL_BASE + 0x309C) // 309C
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_ADDR            (WF_PHYRX_CTRL_BASE + 0x30A0) // 30A0
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_ADDR          (WF_PHYRX_CTRL_BASE + 0x3900) // 3900
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_ADDR          (WF_PHYRX_CTRL_BASE + 0x3904) // 3904
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_2_ADDR          (WF_PHYRX_CTRL_BASE + 0x3910) // 3910
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_3_ADDR          (WF_PHYRX_CTRL_BASE + 0x3914) // 3914
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_4_ADDR          (WF_PHYRX_CTRL_BASE + 0x3918) // 3918
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_5_ADDR          (WF_PHYRX_CTRL_BASE + 0x391C) // 391C
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_ADDR   (WF_PHYRX_CTRL_BASE + 0x3928) // 3928
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_ADDR      (WF_PHYRX_CTRL_BASE + 0x3A3C) // 3A3C
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_ADDR    (WF_PHYRX_CTRL_BASE + 0x3A40) // 3A40
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV0_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A44) // 3A44
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV1_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A48) // 3A48
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV2_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A4C) // 3A4C
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV3_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A50) // 3A50
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV4_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A54) // 3A54
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV5_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A58) // 3A58
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV6_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A5C) // 3A5C
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_1_ADDR    (WF_PHYRX_CTRL_BASE + 0x3A60) // 3A60
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_2_ADDR    (WF_PHYRX_CTRL_BASE + 0x3A64) // 3A64
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_3_ADDR    (WF_PHYRX_CTRL_BASE + 0x3A68) // 3A68
#define WF_PHYRX_CTRL_CR_BAND1_TXV_ERR_MASK_ADDR               (WF_PHYRX_CTRL_BASE + 0x3A6C) // 3A6C
#define WF_PHYRX_CTRL_RO_BAND1_TXV_PKT_CNT_ADDR                (WF_PHYRX_CTRL_BASE + 0x3A70) // 3A70
#define WF_PHYRX_CTRL_RO_BAND1_TXV_1_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3A74) // 3A74
#define WF_PHYRX_CTRL_RO_BAND1_TXV_2_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3A78) // 3A78
#define WF_PHYRX_CTRL_RO_BAND1_TXV_3_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3A7C) // 3A7C
#define WF_PHYRX_CTRL_RO_BAND1_TXV_4_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3A80) // 3A80
#define WF_PHYRX_CTRL_RO_BAND1_TXV_5_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3A84) // 3A84
#define WF_PHYRX_CTRL_RO_BAND1_TXV_6_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3A88) // 3A88
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_TXD_ADDR          (WF_PHYRX_CTRL_BASE + 0x3A8C) // 3A8C
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_0_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A90) // 3A90
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_1_ADDR         (WF_PHYRX_CTRL_BASE + 0x3A94) // 3A94
#define WF_PHYRX_CTRL_RO_BAND1_TXV_ERR_MASK_ADDR               (WF_PHYRX_CTRL_BASE + 0x3A98) // 3A98
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR                  (WF_PHYRX_CTRL_BASE + 0x3AB0) // 3AB0
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_ADDR                  (WF_PHYRX_CTRL_BASE + 0x3AB4) // 3AB4
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_ADDR                  (WF_PHYRX_CTRL_BASE + 0x3AB8) // 3AB8
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_ADDR                   (WF_PHYRX_CTRL_BASE + 0x3ABC) // 3ABC
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_ADDR    (WF_PHYRX_CTRL_BASE + 0x3AC0) // 3AC0
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_1_ADDR    (WF_PHYRX_CTRL_BASE + 0x3AC4) // 3AC4
#define WF_PHYRX_CTRL_RO_BAND1_RXV_0_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AD0) // 3AD0
#define WF_PHYRX_CTRL_RO_BAND1_RXV_1_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AD4) // 3AD4
#define WF_PHYRX_CTRL_RO_BAND1_RXV_2_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AD8) // 3AD8
#define WF_PHYRX_CTRL_RO_BAND1_RXV_3_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3ADC) // 3ADC
#define WF_PHYRX_CTRL_RO_BAND1_RXV_4_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AE0) // 3AE0
#define WF_PHYRX_CTRL_RO_BAND1_RXV_5_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AE4) // 3AE4
#define WF_PHYRX_CTRL_RO_BAND1_RXV_6_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AE8) // 3AE8
#define WF_PHYRX_CTRL_RO_BAND1_RXV_7_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AEC) // 3AEC
#define WF_PHYRX_CTRL_RO_BAND1_RXV_8_ADDR                      (WF_PHYRX_CTRL_BASE + 0x3AF0) // 3AF0
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD0_ADDR               (WF_PHYRX_CTRL_BASE + 0x3B00) // 3B00
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD1_ADDR               (WF_PHYRX_CTRL_BASE + 0x3B04) // 3B04
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4000) // 4000
#define WF_PHYRX_CTRL_CR_MBIST_DIAG_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4004) // 4004
#define WF_PHYRX_CTRL_CR_MBIST_BSEL_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4008) // 4008
#define WF_PHYRX_CTRL_CR_MBIST_BACKGROUND_ADDR                 (WF_PHYRX_CTRL_BASE + 0x400C) // 400C
#define WF_PHYRX_CTRL_CR_MBIST_MODE_0_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4020) // 4020
#define WF_PHYRX_CTRL_CR_MBIST_MODE_1_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4024) // 4024
#define WF_PHYRX_CTRL_CR_MBIST_MODE_2_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4028) // 4028
#define WF_PHYRX_CTRL_CR_MBIST_MODE_3_ADDR                     (WF_PHYRX_CTRL_BASE + 0x402C) // 402C
#define WF_PHYRX_CTRL_CR_MBIST_MODE_4_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4030) // 4030
#define WF_PHYRX_CTRL_CR_MBIST_MODE_5_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4034) // 4034
#define WF_PHYRX_CTRL_RO_MBIST_DONE_0_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4040) // 4040
#define WF_PHYRX_CTRL_RO_MBIST_DONE_1_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4044) // 4044
#define WF_PHYRX_CTRL_RO_MBIST_DONE_2_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4048) // 4048
#define WF_PHYRX_CTRL_RO_MBIST_DONE_3_ADDR                     (WF_PHYRX_CTRL_BASE + 0x404C) // 404C
#define WF_PHYRX_CTRL_RO_MBIST_DONE_4_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4050) // 4050
#define WF_PHYRX_CTRL_RO_MBIST_DONE_5_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4054) // 4054
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_0_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4060) // 4060
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_1_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4064) // 4064
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_2_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4068) // 4068
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_3_ADDR                     (WF_PHYRX_CTRL_BASE + 0x406C) // 406C
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_4_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4070) // 4070
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_5_ADDR                     (WF_PHYRX_CTRL_BASE + 0x4074) // 4074
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_0_ADDR             (WF_PHYRX_CTRL_BASE + 0x4080) // 4080
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_1_ADDR             (WF_PHYRX_CTRL_BASE + 0x4084) // 4084
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_2_ADDR             (WF_PHYRX_CTRL_BASE + 0x4088) // 4088
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_3_ADDR             (WF_PHYRX_CTRL_BASE + 0x408C) // 408C
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_4_ADDR             (WF_PHYRX_CTRL_BASE + 0x4090) // 4090
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_5_ADDR             (WF_PHYRX_CTRL_BASE + 0x4094) // 4094
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_0_ADDR               (WF_PHYRX_CTRL_BASE + 0x4200) // 4200
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_1_ADDR               (WF_PHYRX_CTRL_BASE + 0x4204) // 4204
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_2_ADDR               (WF_PHYRX_CTRL_BASE + 0x4208) // 4208
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_3_ADDR               (WF_PHYRX_CTRL_BASE + 0x420C) // 420C
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_4_ADDR               (WF_PHYRX_CTRL_BASE + 0x4210) // 4210
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_5_ADDR               (WF_PHYRX_CTRL_BASE + 0x4214) // 4214
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_6_ADDR               (WF_PHYRX_CTRL_BASE + 0x4218) // 4218
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_7_ADDR               (WF_PHYRX_CTRL_BASE + 0x421C) // 421C
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_8_ADDR               (WF_PHYRX_CTRL_BASE + 0x4220) // 4220
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_9_ADDR               (WF_PHYRX_CTRL_BASE + 0x4224) // 4224
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_10_ADDR              (WF_PHYRX_CTRL_BASE + 0x4228) // 4228
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_11_ADDR              (WF_PHYRX_CTRL_BASE + 0x422C) // 422C
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_12_ADDR              (WF_PHYRX_CTRL_BASE + 0x4230) // 4230
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_13_ADDR              (WF_PHYRX_CTRL_BASE + 0x4234) // 4234
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_14_ADDR              (WF_PHYRX_CTRL_BASE + 0x4238) // 4238
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_15_ADDR              (WF_PHYRX_CTRL_BASE + 0x423C) // 423C
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_16_ADDR              (WF_PHYRX_CTRL_BASE + 0x4240) // 4240
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_17_ADDR              (WF_PHYRX_CTRL_BASE + 0x4244) // 4244
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_18_ADDR              (WF_PHYRX_CTRL_BASE + 0x4248) // 4248
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_19_ADDR              (WF_PHYRX_CTRL_BASE + 0x424C) // 424C
#define WF_PHYRX_CTRL_CR_BAND0_M2M_PHY_INTF_ADDR               (WF_PHYRX_CTRL_BASE + 0x4700) // 4700
#define WF_PHYRX_CTRL_RO_BAND0_M2M_PHY_INTF_ADDR               (WF_PHYRX_CTRL_BASE + 0x4704) // 4704
#define WF_PHYRX_CTRL_RO_BAND0_M2M_RX_DBG_STATUS_ADDR          (WF_PHYRX_CTRL_BASE + 0x4708) // 4708
#define WF_PHYRX_CTRL_RO_BAND0_M2M_TX_DBG_STATUS_ADDR          (WF_PHYRX_CTRL_BASE + 0x470C) // 470C
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV3_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4720) // 4720
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV4_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4724) // 4724
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV5_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4728) // 4728
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV6_ADDR                  (WF_PHYRX_CTRL_BASE + 0x472C) // 472C
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV1_ADDR              (WF_PHYRX_CTRL_BASE + 0x4730) // 4730
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV2_ADDR              (WF_PHYRX_CTRL_BASE + 0x4734) // 4734
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_CCK_PER_ADDR               (WF_PHYRX_CTRL_BASE + 0x4738) // 4738
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_LG_PER_ADDR                (WF_PHYRX_CTRL_BASE + 0x473C) // 473C
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER0_ADDR             (WF_PHYRX_CTRL_BASE + 0x4740) // 4740
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER1_ADDR             (WF_PHYRX_CTRL_BASE + 0x4744) // 4744
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER0_ADDR             (WF_PHYRX_CTRL_BASE + 0x4748) // 4748
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER1_ADDR             (WF_PHYRX_CTRL_BASE + 0x474C) // 474C
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER0_ADDR            (WF_PHYRX_CTRL_BASE + 0x4750) // 4750
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER1_ADDR            (WF_PHYRX_CTRL_BASE + 0x4754) // 4754
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER0_ADDR           (WF_PHYRX_CTRL_BASE + 0x4758) // 4758
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER1_ADDR           (WF_PHYRX_CTRL_BASE + 0x475C) // 475C
#define WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4800) // 4800
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4804) // 4804
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_0_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4808) // 4808
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x480C) // 480C
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4810) // 4810
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_3_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4814) // 4814
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_4_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4818) // 4818
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_5_ADDR                 (WF_PHYRX_CTRL_BASE + 0x481C) // 481C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_0_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4820) // 4820
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4824) // 4824
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4828) // 4828
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_3_ADDR                 (WF_PHYRX_CTRL_BASE + 0x482C) // 482C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_4_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4830) // 4830
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_5_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4834) // 4834
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_6_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4838) // 4838
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR                  (WF_PHYRX_CTRL_BASE + 0x483C) // 483C
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_ADDR                      (WF_PHYRX_CTRL_BASE + 0x4840) // 4840
#define WF_PHYRX_CTRL_RO_BF_STATUS_ADDR                        (WF_PHYRX_CTRL_BASE + 0x4844) // 4844
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_0_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4848) // 4848
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_1_ADDR                 (WF_PHYRX_CTRL_BASE + 0x484C) // 484C
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_2_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4850) // 4850
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_ADDR            (WF_PHYRX_CTRL_BASE + 0x4854) // 4854
#define WF_PHYRX_CTRL_CR_BF_SVD_0_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4858) // 4858
#define WF_PHYRX_CTRL_CR_BF_SVD_1_ADDR                         (WF_PHYRX_CTRL_BASE + 0x485C) // 485C
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x4860) // 4860
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x4864) // 4864
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_0_ADDR            (WF_PHYRX_CTRL_BASE + 0x4868) // 4868
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_1_ADDR            (WF_PHYRX_CTRL_BASE + 0x486C) // 486C
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_0_ADDR            (WF_PHYRX_CTRL_BASE + 0x4870) // 4870
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_1_ADDR            (WF_PHYRX_CTRL_BASE + 0x4874) // 4874
#define WF_PHYRX_CTRL_RO_MUTX_STATUS_ADDR                      (WF_PHYRX_CTRL_BASE + 0x4878) // 4878
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x487C) // 487C
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x4880) // 4880
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x4884) // 4884
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x4888) // 4888
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x488C) // 488C
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_ADDR              (WF_PHYRX_CTRL_BASE + 0x4890) // 4890
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_ADDR                   (WF_PHYRX_CTRL_BASE + 0x489C) // 489C
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_ADDR                   (WF_PHYRX_CTRL_BASE + 0x48A0) // 48A0
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_ADDR              (WF_PHYRX_CTRL_BASE + 0x48A4) // 48A4
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_0_ADDR           (WF_PHYRX_CTRL_BASE + 0x48A8) // 48A8
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_1_ADDR           (WF_PHYRX_CTRL_BASE + 0x48AC) // 48AC
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_0_ADDR            (WF_PHYRX_CTRL_BASE + 0x48B0) // 48B0
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_1_ADDR            (WF_PHYRX_CTRL_BASE + 0x48B4) // 48B4
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_3_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48B8) // 48B8
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_4_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48BC) // 48BC
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_5_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48C0) // 48C0
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR             (WF_PHYRX_CTRL_BASE + 0x48C8) // 48C8
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_ADDR               (WF_PHYRX_CTRL_BASE + 0x48CC) // 48CC
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_6_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48D0) // 48D0
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_7_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48D4) // 48D4
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_8_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48D8) // 48D8
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_9_ADDR                 (WF_PHYRX_CTRL_BASE + 0x48DC) // 48DC
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_10_ADDR                (WF_PHYRX_CTRL_BASE + 0x48E0) // 48E0
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_11_ADDR                (WF_PHYRX_CTRL_BASE + 0x48E4) // 48E4
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_12_ADDR                (WF_PHYRX_CTRL_BASE + 0x48E8) // 48E8
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_13_ADDR                (WF_PHYRX_CTRL_BASE + 0x48EC) // 48EC
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_14_ADDR                (WF_PHYRX_CTRL_BASE + 0x48F0) // 48F0
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_15_ADDR                (WF_PHYRX_CTRL_BASE + 0x48F4) // 48F4
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_16_ADDR                (WF_PHYRX_CTRL_BASE + 0x48F8) // 48F8
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_17_ADDR                (WF_PHYRX_CTRL_BASE + 0x48FC) // 48FC
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_18_ADDR                (WF_PHYRX_CTRL_BASE + 0x4900) // 4900
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_19_ADDR                (WF_PHYRX_CTRL_BASE + 0x4904) // 4904
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_20_ADDR                (WF_PHYRX_CTRL_BASE + 0x4908) // 4908
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_21_ADDR                (WF_PHYRX_CTRL_BASE + 0x490C) // 490C
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_22_ADDR                (WF_PHYRX_CTRL_BASE + 0x4910) // 4910
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_23_ADDR                (WF_PHYRX_CTRL_BASE + 0x4914) // 4914
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_24_ADDR                (WF_PHYRX_CTRL_BASE + 0x4918) // 4918
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_25_ADDR                (WF_PHYRX_CTRL_BASE + 0x491C) // 491C
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_26_ADDR                (WF_PHYRX_CTRL_BASE + 0x4920) // 4920
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_27_ADDR                (WF_PHYRX_CTRL_BASE + 0x4924) // 4924
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_0_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4928) // 4928
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_1_ADDR                  (WF_PHYRX_CTRL_BASE + 0x492C) // 492C
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_2_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4930) // 4930
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_3_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4934) // 4934
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_4_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4938) // 4938
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_7_ADDR                 (WF_PHYRX_CTRL_BASE + 0x493C) // 493C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_8_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4940) // 4940
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_9_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4944) // 4944
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_10_ADDR                (WF_PHYRX_CTRL_BASE + 0x4948) // 4948
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_11_ADDR                (WF_PHYRX_CTRL_BASE + 0x494C) // 494C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_12_ADDR                (WF_PHYRX_CTRL_BASE + 0x4950) // 4950
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_13_ADDR                (WF_PHYRX_CTRL_BASE + 0x4954) // 4954
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_14_ADDR                (WF_PHYRX_CTRL_BASE + 0x4958) // 4958
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_15_ADDR                (WF_PHYRX_CTRL_BASE + 0x495C) // 495C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_16_ADDR                (WF_PHYRX_CTRL_BASE + 0x4960) // 4960
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_17_ADDR                (WF_PHYRX_CTRL_BASE + 0x4964) // 4964
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_18_ADDR                (WF_PHYRX_CTRL_BASE + 0x4968) // 4968
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_19_ADDR                (WF_PHYRX_CTRL_BASE + 0x496C) // 496C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_20_ADDR                (WF_PHYRX_CTRL_BASE + 0x4970) // 4970
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_21_ADDR                (WF_PHYRX_CTRL_BASE + 0x4974) // 4974
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_22_ADDR                (WF_PHYRX_CTRL_BASE + 0x4978) // 4978
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_23_ADDR                (WF_PHYRX_CTRL_BASE + 0x497C) // 497C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_24_ADDR                (WF_PHYRX_CTRL_BASE + 0x4980) // 4980
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_25_ADDR                (WF_PHYRX_CTRL_BASE + 0x4984) // 4984
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_26_ADDR                (WF_PHYRX_CTRL_BASE + 0x4988) // 4988
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_27_ADDR                (WF_PHYRX_CTRL_BASE + 0x498C) // 498C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_28_ADDR                (WF_PHYRX_CTRL_BASE + 0x4990) // 4990
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_29_ADDR                (WF_PHYRX_CTRL_BASE + 0x4994) // 4994
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_30_ADDR                (WF_PHYRX_CTRL_BASE + 0x4998) // 4998
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_31_ADDR                (WF_PHYRX_CTRL_BASE + 0x499C) // 499C
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_32_ADDR                (WF_PHYRX_CTRL_BASE + 0x49A0) // 49A0
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_6_ADDR                 (WF_PHYRX_CTRL_BASE + 0x49A4) // 49A4
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_7_ADDR                 (WF_PHYRX_CTRL_BASE + 0x49A8) // 49A8
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_8_ADDR                 (WF_PHYRX_CTRL_BASE + 0x49AC) // 49AC
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_9_ADDR                 (WF_PHYRX_CTRL_BASE + 0x49B0) // 49B0
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_10_ADDR                (WF_PHYRX_CTRL_BASE + 0x49B4) // 49B4
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_11_ADDR                (WF_PHYRX_CTRL_BASE + 0x49B8) // 49B8
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_12_ADDR                (WF_PHYRX_CTRL_BASE + 0x49BC) // 49BC
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_13_ADDR                (WF_PHYRX_CTRL_BASE + 0x49C0) // 49C0
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_14_ADDR                (WF_PHYRX_CTRL_BASE + 0x49C4) // 49C4
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_15_ADDR                (WF_PHYRX_CTRL_BASE + 0x49C8) // 49C8
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_16_ADDR                (WF_PHYRX_CTRL_BASE + 0x49CC) // 49CC
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_17_ADDR                (WF_PHYRX_CTRL_BASE + 0x49D0) // 49D0
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_18_ADDR                (WF_PHYRX_CTRL_BASE + 0x49D4) // 49D4
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_19_ADDR                (WF_PHYRX_CTRL_BASE + 0x49D8) // 49D8
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_20_ADDR                (WF_PHYRX_CTRL_BASE + 0x49DC) // 49DC
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_21_ADDR                (WF_PHYRX_CTRL_BASE + 0x49E0) // 49E0
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_22_ADDR                (WF_PHYRX_CTRL_BASE + 0x49E4) // 49E4
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_23_ADDR                (WF_PHYRX_CTRL_BASE + 0x49E8) // 49E8
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_24_ADDR                (WF_PHYRX_CTRL_BASE + 0x49EC) // 49EC
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_25_ADDR                (WF_PHYRX_CTRL_BASE + 0x49F0) // 49F0
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_26_ADDR                (WF_PHYRX_CTRL_BASE + 0x49F4) // 49F4
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_27_ADDR                (WF_PHYRX_CTRL_BASE + 0x49F8) // 49F8
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_28_ADDR                (WF_PHYRX_CTRL_BASE + 0x49FC) // 49FC
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_29_ADDR                (WF_PHYRX_CTRL_BASE + 0x4A00) // 4A00
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_ADDR               (WF_PHYRX_CTRL_BASE + 0x4A04) // 4A04
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR2_ADDR               (WF_PHYRX_CTRL_BASE + 0x4A08) // 4A08
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_1_ADDR            (WF_PHYRX_CTRL_BASE + 0x4A0C) // 4A0C
#define WF_PHYRX_CTRL_CR_BF_SVD_2_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C00) // 4C00
#define WF_PHYRX_CTRL_CR_BF_SVD_3_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C04) // 4C04
#define WF_PHYRX_CTRL_CR_BF_SVD_4_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C08) // 4C08
#define WF_PHYRX_CTRL_CR_BF_SVD_5_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C0C) // 4C0C
#define WF_PHYRX_CTRL_CR_BF_SVD_6_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C10) // 4C10
#define WF_PHYRX_CTRL_CR_BF_SVD_7_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C14) // 4C14
#define WF_PHYRX_CTRL_CR_BF_SVD_8_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C18) // 4C18
#define WF_PHYRX_CTRL_CR_BF_SVD_9_ADDR                         (WF_PHYRX_CTRL_BASE + 0x4C1C) // 4C1C
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR                   (WF_PHYRX_CTRL_BASE + 0x4C20) // 4C20
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_ADDR                        (WF_PHYRX_CTRL_BASE + 0x4C24) // 4C24
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR                        (WF_PHYRX_CTRL_BASE + 0x4C28) // 4C28
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR                        (WF_PHYRX_CTRL_BASE + 0x4C2C) // 4C2C
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR                        (WF_PHYRX_CTRL_BASE + 0x4C30) // 4C30
#define WF_PHYRX_CTRL_CR_MUTX_PN_ADDR                          (WF_PHYRX_CTRL_BASE + 0x4C34) // 4C34
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_ADDR                  (WF_PHYRX_CTRL_BASE + 0x4C38) // 4C38
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_ADDR                    (WF_PHYRX_CTRL_BASE + 0x4C3C) // 4C3C
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_ADDR                   (WF_PHYRX_CTRL_BASE + 0x4C40) // 4C40
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_ADDR             (WF_PHYRX_CTRL_BASE + 0x4CC4) // 4CC4
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_ADDR                 (WF_PHYRX_CTRL_BASE + 0x4CC8) // 4CC8
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_ADDR             (WF_PHYRX_CTRL_BASE + 0x4CCC) // 4CCC
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_ADDR            (WF_PHYRX_CTRL_BASE + 0x4CD0) // 4CD0
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4CD4) // 4CD4
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4CD8) // 4CD8
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4CDC) // 4CDC
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4CE0) // 4CE0
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4CE4) // 4CE4
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_ADDR                       (WF_PHYRX_CTRL_BASE + 0x4CE8) // 4CE8
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR                    (WF_PHYRX_CTRL_BASE + 0x4CEC) // 4CEC




/* =====================================================================================

  ---CR_PHYSYS_CTRL (0x82000000 + 0x000)---

    CR_PHY_PLLSRC_MODE[1..0]     - (RW) 0: Divide-by-1
                                     1: Divide-by-2
                                     2: Divide-by-4
                                     3: Divide-by-8
    CR_PD_IS_CCK_GATE[2]         - (RW) [DE] BBP control CR
    CR_APBBRG_PCLK_FREE_RUN[3]   - (RW) [DE] BBP control CR
    CR_BAND0_RFINTF_CAL_NSS[5..4] - (RW) [DE] BBP control CR
    CR_BAND1_RFINTF_CAL_NSS[7..6] - (RW) [DE] BBP control CR
    CR_BAND0_VAR_CKCTL[11..8]    - (RW) [DE] BBP control CR
    CR_RXAFIFO_VAR_CKCTL[12]     - (RW) [DE] BBP control CR
                                     1: 320M clock
                                     0: 160M clock
    RESERVED13[27..13]           - (RO) Reserved bits
    CR_CCK_BAND0_BAND1[28]       - (RW) [DE] BBP control CR
    CR_CCK_SKIP_SHORT_ERR[29]    - (RW) [DE] BBP control CR
    CR_MODE_RSVD[30]             - (RW) [DE] BBP control CR
    CR_DBDC_MODE[31]             - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_DBDC_MODE_ADDR         WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_DBDC_MODE_MASK         0x80000000                // CR_DBDC_MODE[31]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_DBDC_MODE_SHFT         31
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_MODE_RSVD_ADDR         WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_MODE_RSVD_MASK         0x40000000                // CR_MODE_RSVD[30]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_MODE_RSVD_SHFT         30
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_CCK_SKIP_SHORT_ERR_ADDR WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_CCK_SKIP_SHORT_ERR_MASK 0x20000000                // CR_CCK_SKIP_SHORT_ERR[29]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_CCK_SKIP_SHORT_ERR_SHFT 29
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_CCK_BAND0_BAND1_ADDR   WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_CCK_BAND0_BAND1_MASK   0x10000000                // CR_CCK_BAND0_BAND1[28]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_CCK_BAND0_BAND1_SHFT   28
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_RXAFIFO_VAR_CKCTL_ADDR WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_RXAFIFO_VAR_CKCTL_MASK 0x00001000                // CR_RXAFIFO_VAR_CKCTL[12]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_RXAFIFO_VAR_CKCTL_SHFT 12
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND0_VAR_CKCTL_ADDR   WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND0_VAR_CKCTL_MASK   0x00000F00                // CR_BAND0_VAR_CKCTL[11..8]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND0_VAR_CKCTL_SHFT   8
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND1_RFINTF_CAL_NSS_ADDR WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND1_RFINTF_CAL_NSS_MASK 0x000000C0                // CR_BAND1_RFINTF_CAL_NSS[7..6]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND1_RFINTF_CAL_NSS_SHFT 6
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND0_RFINTF_CAL_NSS_ADDR WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND0_RFINTF_CAL_NSS_MASK 0x00000030                // CR_BAND0_RFINTF_CAL_NSS[5..4]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_BAND0_RFINTF_CAL_NSS_SHFT 4
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_APBBRG_PCLK_FREE_RUN_ADDR WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_APBBRG_PCLK_FREE_RUN_MASK 0x00000008                // CR_APBBRG_PCLK_FREE_RUN[3]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_APBBRG_PCLK_FREE_RUN_SHFT 3
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_PD_IS_CCK_GATE_ADDR    WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_PD_IS_CCK_GATE_MASK    0x00000004                // CR_PD_IS_CCK_GATE[2]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_PD_IS_CCK_GATE_SHFT    2
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_PHY_PLLSRC_MODE_ADDR   WF_PHYRX_CTRL_CR_PHYSYS_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_PHY_PLLSRC_MODE_MASK   0x00000003                // CR_PHY_PLLSRC_MODE[1..0]
#define WF_PHYRX_CTRL_CR_PHYSYS_CTRL_CR_PHY_PLLSRC_MODE_SHFT   0

/* =====================================================================================

  ---CR_PHYCK_STREAM_MAP (0x82000000 + 0x004)---

    CR_PHYCK_SS_MAP_WF0[2..0]    - (RW) 0: Band0 WF0, 1: Band0 WF1, 2: Band0 WF2, 3: Band0 WF3
                                     4: Band1 WF0, 5: Band1 WF1, 6: Band1 WF2, 7: Band1 WF3
    RESERVED3[3]                 - (RO) Reserved bits
    CR_PHYCK_SS_MAP_WF1[6..4]    - (RW) 0: Band0 WF0, 1: Band0 WF1, 2: Band0 WF2, 3: Band0 WF3
                                     4: Band1 WF0, 5: Band1 WF1, 6: Band1 WF2, 7: Band1 WF3
    RESERVED7[7]                 - (RO) Reserved bits
    CR_PHYCK_SS_MAP_WF2[10..8]   - (RW) 0: Band0 WF0, 1: Band0 WF1, 2: Band0 WF2, 3: Band0 WF3
                                     4: Band1 WF0, 5: Band1 WF1, 6: Band1 WF2, 7: Band1 WF3
    RESERVED11[11]               - (RO) Reserved bits
    CR_PHYCK_SS_MAP_WF3[14..12]  - (RW) 0: Band0 WF0, 1: Band0 WF1, 2: Band0 WF2, 3: Band0 WF3
                                     4: Band1 WF0, 5: Band1 WF1, 6: Band1 WF2, 7: Band1 WF3
    RESERVED15[15]               - (RO) Reserved bits
    CR_PHYRST_OUTER_ES_MAP[19..16] - (RW) 0: ES0, 1: ES1, 2: ES2, 3: ES3
    CR_PHYRST_OUTER_SS_MAP[23..20] - (RW) 0: SS0, 1: SS1, 2: SS2, 3: SS3
    CR_PHYRST_LDPC_DEC_MAP[27..24] - (RW) 0: DEC0, 1: DEC1, 2:DEC2, 3DEC3
    CR_PHYCK_DEBUG_ENAB[28]      - (RW) 1: Enable Debug Clock Toggles
                                     0: Disable Debug Clock toggles
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_DEBUG_ENAB_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_DEBUG_ENAB_MASK 0x10000000                // CR_PHYCK_DEBUG_ENAB[28]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_DEBUG_ENAB_SHFT 28
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_LDPC_DEC_MAP_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_LDPC_DEC_MAP_MASK 0x0F000000                // CR_PHYRST_LDPC_DEC_MAP[27..24]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_LDPC_DEC_MAP_SHFT 24
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_OUTER_SS_MAP_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_OUTER_SS_MAP_MASK 0x00F00000                // CR_PHYRST_OUTER_SS_MAP[23..20]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_OUTER_SS_MAP_SHFT 20
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_OUTER_ES_MAP_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_OUTER_ES_MAP_MASK 0x000F0000                // CR_PHYRST_OUTER_ES_MAP[19..16]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYRST_OUTER_ES_MAP_SHFT 16
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF3_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF3_MASK 0x00007000                // CR_PHYCK_SS_MAP_WF3[14..12]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF3_SHFT 12
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF2_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF2_MASK 0x00000700                // CR_PHYCK_SS_MAP_WF2[10..8]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF2_SHFT 8
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF1_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF1_MASK 0x00000070                // CR_PHYCK_SS_MAP_WF1[6..4]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF1_SHFT 4
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF0_ADDR WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF0_MASK 0x00000007                // CR_PHYCK_SS_MAP_WF0[2..0]
#define WF_PHYRX_CTRL_CR_PHYCK_STREAM_MAP_CR_PHYCK_SS_MAP_WF0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCK_MANU_MODE (0x82000000 + 0x008)---

    CR_BAND0_PHYCK_MANU_MODE[23..0] - (RW) 0: HW Mode
                                     1: Manual Mode
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_MODE_CR_BAND0_PHYCK_MANU_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_MODE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_MODE_CR_BAND0_PHYCK_MANU_MODE_MASK 0x00FFFFFF                // CR_BAND0_PHYCK_MANU_MODE[23..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_MODE_CR_BAND0_PHYCK_MANU_MODE_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCK_MANU_ENAB (0x82000000 + 0x00C)---

    CR_BAND0_PHYCK_MANU_ENAB[23..0] - (RW) 0: HW Mode
                                     1: Manual Mode
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_ENAB_CR_BAND0_PHYCK_MANU_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_ENAB_CR_BAND0_PHYCK_MANU_ENAB_MASK 0x00FFFFFF                // CR_BAND0_PHYCK_MANU_ENAB[23..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCK_MANU_ENAB_CR_BAND0_PHYCK_MANU_ENAB_SHFT 0

/* =====================================================================================

  ---CR_BAND0_OPOST_VARCK_TABLE (0x82000000 + 0x010)---

    CR_BAND0_OPOST_VARCK_TAB[15..0] - (RW) 0: Down-sampling by half
                                     1: Maximum Speed
    CR_BAND0_MIMOD_VARCK_TAB[31..16] - (RW) 0: Down-sampling by half
                                     1: Maximum Speed

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_CR_BAND0_MIMOD_VARCK_TAB_ADDR WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_CR_BAND0_MIMOD_VARCK_TAB_MASK 0xFFFF0000                // CR_BAND0_MIMOD_VARCK_TAB[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_CR_BAND0_MIMOD_VARCK_TAB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_CR_BAND0_OPOST_VARCK_TAB_ADDR WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_CR_BAND0_OPOST_VARCK_TAB_MASK 0x0000FFFF                // CR_BAND0_OPOST_VARCK_TAB[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_OPOST_VARCK_TABLE_CR_BAND0_OPOST_VARCK_TAB_SHFT 0

/* =====================================================================================

  ---CR_BAND0_OUTER_VARCK_TABLE (0x82000000 + 0x014)---

    CR_BAND0_OUTER_VARCK_TAB[15..0] - (RW) 0: Down-sampling by half
                                     1: Maximum Speed
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_OUTER_VARCK_TABLE_CR_BAND0_OUTER_VARCK_TAB_ADDR WF_PHYRX_CTRL_CR_BAND0_OUTER_VARCK_TABLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_OUTER_VARCK_TABLE_CR_BAND0_OUTER_VARCK_TAB_MASK 0x0000FFFF                // CR_BAND0_OUTER_VARCK_TAB[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_OUTER_VARCK_TABLE_CR_BAND0_OUTER_VARCK_TAB_SHFT 0

/* =====================================================================================

  ---CR_BAND0_RST_CTRL (0x82000000 + 0x020)---

    CR_BAND0_RFINTF_LOGRST[0]    - (RW) 1: Reset
    CR_BAND0_RXFE_LOGRST[1]      - (RW) 1: Reset
    CR_BAND0_RXTD_LOGRST[2]      - (RW) 1: Reset
    CR_BAND0_FFT_LOGRST[3]       - (RW) 1: Reset
    CR_BAND0_OPOST_LOGRST[4]     - (RW) 1: Reset
    CR_BAND0_PHYMISC_LOGRST[5]   - (RW) 1: Reset
    CR_BAND0_PHYMUX_LOGRST[6]    - (RW) 1: Reset
    CR_BAND0_PHYCTRL_LOGRST[7]   - (RW) 1: Reset
    CR_BAND0_TOAE_LOGRST[8]      - (RW) 1: Reset
    CR_BAND0_TOAE_CAL_LOGRST[9]  - (RW) 1: Reset
    CR_BAND0_RBIST_LOGRST[10]    - (RW) 1: Reset
    CR_BAND0_DPD_CAL_LOGRST[11]  - (RW) 1: Reset
    CR_BAND0_MAC2PHY_LOGRST[12]  - (RW) 1: Reset
    CR_BAND0_RDD_LOGRST[13]      - (RW) 1: Reset
    CR_BAND0_TSSI_LOGRST[14]     - (RW) 1: Reset
    CR_BAND0_TXFE_LOGRST[15]     - (RW) 1: Reset
    CR_BAND0_TXTD_LOGRST[16]     - (RW) 1: Reset
    CR_BAND0_TXFD_LOGRST[17]     - (RW) 1: Reset
    CR_CORDIC_LOGRST[18]         - (RW) 1: Reset
    CR_LDPC_LOGRST[19]           - (RW) 1: Reset
    CR_BCEMULT_LOGRST[20]        - (RW) 1: Reset
    CR_DBGSGD_LOGRST[21]         - (RW) 1: Reset
    CR_PHY_ICAP_LOGRST[22]       - (RW) 1: Reset
    CR_PHY_CSR_LOGRST[23]        - (RW) 1: Reset
    CR_BAND0_RSVD0_LOGRST[24]    - (RW) 1: Reset
    CR_WF0_RFINTF_LOGRST[25]     - (RW) 1: Reset
    CR_WF1_RFINTF_LOGRST[26]     - (RW) 1: Reset
    CR_RFSPI_CSRRST[27]          - (RW) 1: Reset
    CR_BAND0_TXFD_CSRRST[28]     - (RW) 1: Reset (Scrambler)
    CR_BAND0_RFINTF_CSRRST[29]   - (RW) 1: Reset (Reserved)
    CR_BAND0_RXFE_CSRRST[30]     - (RW) 1: Reset (DC Table)
    CR_CORDIC_CSRRST[31]         - (RW) 1: Reset

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_CORDIC_CSRRST_ADDR  WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_CORDIC_CSRRST_MASK  0x80000000                // CR_CORDIC_CSRRST[31]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_CORDIC_CSRRST_SHFT  31
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXFE_CSRRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXFE_CSRRST_MASK 0x40000000                // CR_BAND0_RXFE_CSRRST[30]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXFE_CSRRST_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RFINTF_CSRRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RFINTF_CSRRST_MASK 0x20000000                // CR_BAND0_RFINTF_CSRRST[29]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RFINTF_CSRRST_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFD_CSRRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFD_CSRRST_MASK 0x10000000                // CR_BAND0_TXFD_CSRRST[28]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFD_CSRRST_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_RFSPI_CSRRST_ADDR   WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_RFSPI_CSRRST_MASK   0x08000000                // CR_RFSPI_CSRRST[27]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_RFSPI_CSRRST_SHFT   27
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_WF1_RFINTF_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_WF1_RFINTF_LOGRST_MASK 0x04000000                // CR_WF1_RFINTF_LOGRST[26]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_WF1_RFINTF_LOGRST_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_WF0_RFINTF_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_WF0_RFINTF_LOGRST_MASK 0x02000000                // CR_WF0_RFINTF_LOGRST[25]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_WF0_RFINTF_LOGRST_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RSVD0_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RSVD0_LOGRST_MASK 0x01000000                // CR_BAND0_RSVD0_LOGRST[24]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RSVD0_LOGRST_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_PHY_CSR_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_PHY_CSR_LOGRST_MASK 0x00800000                // CR_PHY_CSR_LOGRST[23]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_PHY_CSR_LOGRST_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_PHY_ICAP_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_PHY_ICAP_LOGRST_MASK 0x00400000                // CR_PHY_ICAP_LOGRST[22]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_PHY_ICAP_LOGRST_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_DBGSGD_LOGRST_ADDR  WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_DBGSGD_LOGRST_MASK  0x00200000                // CR_DBGSGD_LOGRST[21]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_DBGSGD_LOGRST_SHFT  21
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BCEMULT_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BCEMULT_LOGRST_MASK 0x00100000                // CR_BCEMULT_LOGRST[20]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BCEMULT_LOGRST_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_LDPC_LOGRST_ADDR    WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_LDPC_LOGRST_MASK    0x00080000                // CR_LDPC_LOGRST[19]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_LDPC_LOGRST_SHFT    19
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_CORDIC_LOGRST_ADDR  WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_CORDIC_LOGRST_MASK  0x00040000                // CR_CORDIC_LOGRST[18]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_CORDIC_LOGRST_SHFT  18
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFD_LOGRST_MASK 0x00020000                // CR_BAND0_TXFD_LOGRST[17]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFD_LOGRST_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXTD_LOGRST_MASK 0x00010000                // CR_BAND0_TXTD_LOGRST[16]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXTD_LOGRST_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFE_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFE_LOGRST_MASK 0x00008000                // CR_BAND0_TXFE_LOGRST[15]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TXFE_LOGRST_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TSSI_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TSSI_LOGRST_MASK 0x00004000                // CR_BAND0_TSSI_LOGRST[14]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TSSI_LOGRST_SHFT 14
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RDD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RDD_LOGRST_MASK 0x00002000                // CR_BAND0_RDD_LOGRST[13]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RDD_LOGRST_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_MAC2PHY_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_MAC2PHY_LOGRST_MASK 0x00001000                // CR_BAND0_MAC2PHY_LOGRST[12]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_MAC2PHY_LOGRST_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_DPD_CAL_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_DPD_CAL_LOGRST_MASK 0x00000800                // CR_BAND0_DPD_CAL_LOGRST[11]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_DPD_CAL_LOGRST_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RBIST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RBIST_LOGRST_MASK 0x00000400                // CR_BAND0_RBIST_LOGRST[10]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RBIST_LOGRST_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TOAE_CAL_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TOAE_CAL_LOGRST_MASK 0x00000200                // CR_BAND0_TOAE_CAL_LOGRST[9]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TOAE_CAL_LOGRST_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TOAE_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TOAE_LOGRST_MASK 0x00000100                // CR_BAND0_TOAE_LOGRST[8]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_TOAE_LOGRST_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYCTRL_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYCTRL_LOGRST_MASK 0x00000080                // CR_BAND0_PHYCTRL_LOGRST[7]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYCTRL_LOGRST_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYMUX_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYMUX_LOGRST_MASK 0x00000040                // CR_BAND0_PHYMUX_LOGRST[6]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYMUX_LOGRST_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYMISC_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYMISC_LOGRST_MASK 0x00000020                // CR_BAND0_PHYMISC_LOGRST[5]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_PHYMISC_LOGRST_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_OPOST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_OPOST_LOGRST_MASK 0x00000010                // CR_BAND0_OPOST_LOGRST[4]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_OPOST_LOGRST_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_FFT_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_FFT_LOGRST_MASK 0x00000008                // CR_BAND0_FFT_LOGRST[3]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_FFT_LOGRST_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXTD_LOGRST_MASK 0x00000004                // CR_BAND0_RXTD_LOGRST[2]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXTD_LOGRST_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXFE_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXFE_LOGRST_MASK 0x00000002                // CR_BAND0_RXFE_LOGRST[1]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RXFE_LOGRST_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RFINTF_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RFINTF_LOGRST_MASK 0x00000001                // CR_BAND0_RFINTF_LOGRST[0]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_CR_BAND0_RFINTF_LOGRST_SHFT 0

/* =====================================================================================

  ---CR_BAND0_RST_CTRL_1 (0x82000000 + 0x0024)---

    CR_BAND0_PHYRST_DISABLE_CTL[7..0] - (RW) [DE] BBP control CR
    CR_BAND0_PTA_SX_2WF[8]       - (RW) [DE] BBP control CR
    CR_BAND0_PTA_SX_2WF_MANU[9]  - (RW) [DE] BBP control CR
    RESERVED10[27..10]           - (RO) Reserved bits
    CR_WF0_RXTD_LOGRST[28]       - (RW) 1: Reset
    CR_WF1_RXTD_LOGRST[29]       - (RW) 1: Reset
    CR_WF2_RXTD_LOGRST[30]       - (RW) 1: Reset
    CR_WF3_RXTD_LOGRST[31]       - (RW) 1: Reset

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF3_RXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF3_RXTD_LOGRST_MASK 0x80000000                // CR_WF3_RXTD_LOGRST[31]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF3_RXTD_LOGRST_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF2_RXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF2_RXTD_LOGRST_MASK 0x40000000                // CR_WF2_RXTD_LOGRST[30]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF2_RXTD_LOGRST_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF1_RXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF1_RXTD_LOGRST_MASK 0x20000000                // CR_WF1_RXTD_LOGRST[29]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF1_RXTD_LOGRST_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF0_RXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF0_RXTD_LOGRST_MASK 0x10000000                // CR_WF0_RXTD_LOGRST[28]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_WF0_RXTD_LOGRST_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PTA_SX_2WF_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PTA_SX_2WF_MANU_MASK 0x00000200                // CR_BAND0_PTA_SX_2WF_MANU[9]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PTA_SX_2WF_MANU_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PTA_SX_2WF_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PTA_SX_2WF_MASK 0x00000100                // CR_BAND0_PTA_SX_2WF[8]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PTA_SX_2WF_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PHYRST_DISABLE_CTL_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PHYRST_DISABLE_CTL_MASK 0x000000FF                // CR_BAND0_PHYRST_DISABLE_CTL[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_RST_CTRL_1_CR_BAND0_PHYRST_DISABLE_CTL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_TXFD_TXTD_CTRL (0x82000000 + 0x0030)---

    CR_BAND0_DLY_FALL_TXTD[7..0] - (RW) [DE] BBP control CR
    CR_BAND0_DLY_RISE_TXTD[15..8] - (RW) [DE] BBP control CR
    CR_BAND0_DLY_FALL_TXFD[23..16] - (RW) [DE] BBP control CR
    CR_BAND0_DLY_RISE_TXFD[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_RISE_TXFD_ADDR WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_RISE_TXFD_MASK 0xFF000000                // CR_BAND0_DLY_RISE_TXFD[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_RISE_TXFD_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_FALL_TXFD_ADDR WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_FALL_TXFD_MASK 0x00FF0000                // CR_BAND0_DLY_FALL_TXFD[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_FALL_TXFD_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_RISE_TXTD_ADDR WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_RISE_TXTD_MASK 0x0000FF00                // CR_BAND0_DLY_RISE_TXTD[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_RISE_TXTD_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_FALL_TXTD_ADDR WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_FALL_TXTD_MASK 0x000000FF                // CR_BAND0_DLY_FALL_TXTD[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_TXFD_TXTD_CTRL_CR_BAND0_DLY_FALL_TXTD_SHFT 0

/* =====================================================================================

  ---CR_BAND0_MON_FLAG_CTRL1 (0x82000000 + 0x0040)---

    CR_BAND0_MON_LMOD1[7..0]     - (RW) [DE] BBP control CR
    CR_BAND0_MON_HMOD1[15..8]    - (RW) [DE] BBP control CR
    CR_BAND1_MON_LMOD1[23..16]   - (RW) [DE] BBP control CR
    CR_BAND1_MON_HMOD1[31..24]   - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND1_MON_HMOD1_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND1_MON_HMOD1_MASK 0xFF000000                // CR_BAND1_MON_HMOD1[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND1_MON_HMOD1_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND1_MON_LMOD1_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND1_MON_LMOD1_MASK 0x00FF0000                // CR_BAND1_MON_LMOD1[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND1_MON_LMOD1_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND0_MON_HMOD1_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND0_MON_HMOD1_MASK 0x0000FF00                // CR_BAND0_MON_HMOD1[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND0_MON_HMOD1_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND0_MON_LMOD1_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND0_MON_LMOD1_MASK 0x000000FF                // CR_BAND0_MON_LMOD1[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL1_CR_BAND0_MON_LMOD1_SHFT 0

/* =====================================================================================

  ---RO_BAND0_MON_FLAG_STATUS1 (0x82000000 + 0x0048)---

    RO_BAND0_MON_FLAG_STATUS1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS1_RO_BAND0_MON_FLAG_STATUS1_ADDR WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS1_RO_BAND0_MON_FLAG_STATUS1_MASK 0xFFFFFFFF                // RO_BAND0_MON_FLAG_STATUS1[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS1_RO_BAND0_MON_FLAG_STATUS1_SHFT 0

/* =====================================================================================

  ---PHY_DEBUG_SEL (0x82000000 + 0x004C)---

    CR_PHY_DEBUG_MON_SEL[1..0]   - (RW) [DE] BBP control CR
    RESERVED2[3..2]              - (RO) Reserved bits
    CR_BAND0_RX_ERR_WI_TRX[4]    - (RW) [DE] BBP control CR
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_CR_BAND0_RX_ERR_WI_TRX_ADDR WF_PHYRX_CTRL_PHY_DEBUG_SEL_ADDR
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_CR_BAND0_RX_ERR_WI_TRX_MASK 0x00000010                // CR_BAND0_RX_ERR_WI_TRX[4]
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_CR_BAND0_RX_ERR_WI_TRX_SHFT 4
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_CR_PHY_DEBUG_MON_SEL_ADDR  WF_PHYRX_CTRL_PHY_DEBUG_SEL_ADDR
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_CR_PHY_DEBUG_MON_SEL_MASK  0x00000003                // CR_PHY_DEBUG_MON_SEL[1..0]
#define WF_PHYRX_CTRL_PHY_DEBUG_SEL_CR_PHY_DEBUG_MON_SEL_SHFT  0

/* =====================================================================================

  ---CR_PHYCK_DYNAMIC_CTL (0x82000000 + 0x0050)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_POST_MANUAL_MODE_CKEN[16] - (RW) [DE] BBP control CR
    CR_QRD_MANUAL_MODE_CKEN[17]  - (RW) [DE] BBP control CR
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_CR_QRD_MANUAL_MODE_CKEN_ADDR WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_CR_QRD_MANUAL_MODE_CKEN_MASK 0x00020000                // CR_QRD_MANUAL_MODE_CKEN[17]
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_CR_QRD_MANUAL_MODE_CKEN_SHFT 17
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_CR_POST_MANUAL_MODE_CKEN_ADDR WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_CR_POST_MANUAL_MODE_CKEN_MASK 0x00010000                // CR_POST_MANUAL_MODE_CKEN[16]
#define WF_PHYRX_CTRL_CR_PHYCK_DYNAMIC_CTL_CR_POST_MANUAL_MODE_CKEN_SHFT 16

/* =====================================================================================

  ---CR_PHYCK_BAND_CTL (0x82000000 + 0x0054)---

    CR_BAND0_FORCE_CKEN[15..0]   - (RW) [DE] BBP control CR
    CR_BAND1_FORCE_CKEN[31..16]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_CR_BAND1_FORCE_CKEN_ADDR WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_CR_BAND1_FORCE_CKEN_MASK 0xFFFF0000                // CR_BAND1_FORCE_CKEN[31..16]
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_CR_BAND1_FORCE_CKEN_SHFT 16
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_CR_BAND0_FORCE_CKEN_ADDR WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_CR_BAND0_FORCE_CKEN_MASK 0x0000FFFF                // CR_BAND0_FORCE_CKEN[15..0]
#define WF_PHYRX_CTRL_CR_PHYCK_BAND_CTL_CR_BAND0_FORCE_CKEN_SHFT 0

/* =====================================================================================

  ---CR_PHYCK_FFT_DLY_CTL (0x82000000 + 0x0068)---

    CR_BAND_DLY_FALL_FFT[7..0]   - (RW) [DE] BBP control CR
    CR_BAND_DLY_RISE_FFT[15..8]  - (RW) [DE] BBP control CR
    CR_FFT_CK_RST_REV[16]        - (RW) [DE] BBP control CR
    RESERVED17[31..17]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_FFT_CK_RST_REV_ADDR WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_FFT_CK_RST_REV_MASK 0x00010000                // CR_FFT_CK_RST_REV[16]
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_FFT_CK_RST_REV_SHFT 16
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_BAND_DLY_RISE_FFT_ADDR WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_BAND_DLY_RISE_FFT_MASK 0x0000FF00                // CR_BAND_DLY_RISE_FFT[15..8]
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_BAND_DLY_RISE_FFT_SHFT 8
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_BAND_DLY_FALL_FFT_ADDR WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_ADDR
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_BAND_DLY_FALL_FFT_MASK 0x000000FF                // CR_BAND_DLY_FALL_FFT[7..0]
#define WF_PHYRX_CTRL_CR_PHYCK_FFT_DLY_CTL_CR_BAND_DLY_FALL_FFT_SHFT 0

/* =====================================================================================

  ---CR_RST_CTRL_SEL (0x82000000 + 0x0070)---

    CR_TXFE_RST_HW_SEL[0]        - (RW) [DE] BBP control CR
    RESERVED1[7..1]              - (RO) Reserved bits
    CR_CKEN_ACK_LNR_REV[8]       - (RW) [DE] BBP control CR
    CR_DIV_CKEN_CEC_REV[9]       - (RW) [DE] BBP control CR
    CR_PHYMUX_FLG_PA_REV[10]     - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_AB_ERR_PA_REV[12]         - (RW) [DE] BBP control CR
    CR_RX_VLD_PA_REV[13]         - (RW) [DE] BBP control CR
    CR_CKGFSM_PA_REV[14]         - (RW) [DE] BBP control CR
    CR_RX_SIG_PA_REV[15]         - (RW) [DE] BBP control CR
    CR_RBIST_PA_REV[16]          - (RW) [DE] BBP control CR
    RESERVED17[31..17]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RBIST_PA_REV_ADDR     WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RBIST_PA_REV_MASK     0x00010000                // CR_RBIST_PA_REV[16]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RBIST_PA_REV_SHFT     16
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RX_SIG_PA_REV_ADDR    WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RX_SIG_PA_REV_MASK    0x00008000                // CR_RX_SIG_PA_REV[15]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RX_SIG_PA_REV_SHFT    15
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_CKGFSM_PA_REV_ADDR    WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_CKGFSM_PA_REV_MASK    0x00004000                // CR_CKGFSM_PA_REV[14]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_CKGFSM_PA_REV_SHFT    14
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RX_VLD_PA_REV_ADDR    WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RX_VLD_PA_REV_MASK    0x00002000                // CR_RX_VLD_PA_REV[13]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_RX_VLD_PA_REV_SHFT    13
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_AB_ERR_PA_REV_ADDR    WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_AB_ERR_PA_REV_MASK    0x00001000                // CR_AB_ERR_PA_REV[12]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_AB_ERR_PA_REV_SHFT    12
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_PHYMUX_FLG_PA_REV_ADDR WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_PHYMUX_FLG_PA_REV_MASK 0x00000400                // CR_PHYMUX_FLG_PA_REV[10]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_PHYMUX_FLG_PA_REV_SHFT 10
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_DIV_CKEN_CEC_REV_ADDR WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_DIV_CKEN_CEC_REV_MASK 0x00000200                // CR_DIV_CKEN_CEC_REV[9]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_DIV_CKEN_CEC_REV_SHFT 9
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_CKEN_ACK_LNR_REV_ADDR WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_CKEN_ACK_LNR_REV_MASK 0x00000100                // CR_CKEN_ACK_LNR_REV[8]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_CKEN_ACK_LNR_REV_SHFT 8
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_TXFE_RST_HW_SEL_ADDR  WF_PHYRX_CTRL_CR_RST_CTRL_SEL_ADDR
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_TXFE_RST_HW_SEL_MASK  0x00000001                // CR_TXFE_RST_HW_SEL[0]
#define WF_PHYRX_CTRL_CR_RST_CTRL_SEL_CR_TXFE_RST_HW_SEL_SHFT  0

/* =====================================================================================

  ---CR_PWR_ON_BY_PHY_CTRL (0x82000000 + 0x0100)---

    RESERVED0[28..0]             - (RO) Reserved bits
    cr_pwr_on_by_phy_force_value[29] - (RW) cr_pwr_on_by_phy_force_value
    cr_pwr_on_by_phy_force_mode[30] - (RW) cr_pwr_on_by_phy_force_mode
    cr_pwr_on_by_phy_typ_sel[31] - (RW) cr_pwr_on_by_phy_typ_sel

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_typ_sel_ADDR WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_typ_sel_MASK 0x80000000                // cr_pwr_on_by_phy_typ_sel[31]
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_typ_sel_SHFT 31
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_force_mode_ADDR WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_force_mode_MASK 0x40000000                // cr_pwr_on_by_phy_force_mode[30]
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_force_mode_SHFT 30
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_force_value_ADDR WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_force_value_MASK 0x20000000                // cr_pwr_on_by_phy_force_value[29]
#define WF_PHYRX_CTRL_CR_PWR_ON_BY_PHY_CTRL_cr_pwr_on_by_phy_force_value_SHFT 29

/* =====================================================================================

  ---CR_BAND0_MON_FLAG_CTRL (0x82000000 + 0x0200)---

    CR_BAND0_MON_LSEL[7..0]      - (RW) [DE] BBP control CR
    CR_BAND0_MON_HSEL[15..8]     - (RW) [DE] BBP control CR
    CR_BAND0_MON_LMOD0[23..16]   - (RW) [DE] BBP control CR
    CR_BAND0_MON_HMOD0[31..24]   - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_HMOD0_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_HMOD0_MASK 0xFF000000                // CR_BAND0_MON_HMOD0[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_HMOD0_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_LMOD0_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_LMOD0_MASK 0x00FF0000                // CR_BAND0_MON_LMOD0[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_LMOD0_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_HSEL_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_HSEL_MASK 0x0000FF00                // CR_BAND0_MON_HSEL[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_HSEL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_LSEL_ADDR WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_LSEL_MASK 0x000000FF                // CR_BAND0_MON_LSEL[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_MON_FLAG_CTRL_CR_BAND0_MON_LSEL_SHFT 0

/* =====================================================================================

  ---RO_BAND0_MON_FLAG_STATUS (0x82000000 + 0x0204)---

    RO_BAND0_MON_FLAG_STATUS0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS_RO_BAND0_MON_FLAG_STATUS0_ADDR WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS_RO_BAND0_MON_FLAG_STATUS0_MASK 0xFFFFFFFF                // RO_BAND0_MON_FLAG_STATUS0[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_MON_FLAG_STATUS_RO_BAND0_MON_FLAG_STATUS0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_MISC_CTRL (0x82000000 + 0x0208)---

    CR_BAND0_CLR_PHYCTRL_INT[0]  - (RW) [DE] BBP control CR
    CR_BAND0_CLR_WIFI_ERROR_TRIG[1] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD_WAKEUP_IRQ[2] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD_ERROR_IRQ[3] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_MUTX_TX_ERR_EVENT[4] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_MUTX_LQ_ERR_EVENT[5] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_TRX_WDT_TRIG[6] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_SPI_FAIL_IND[7] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_PFMU_IBF_TIMER_EXPIRE[8] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_PFMU_IBF_TIMER_RENEW[9] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD1_WAKEUP_IRQ[10] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD1_ERROR_IRQ[11] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD2_WAKEUP_IRQ[12] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD2_ERROR_IRQ[13] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD3_WAKEUP_IRQ[14] - (RW) [DE] BBP control CR
    CR_BAND0_CLR_RDD3_ERROR_IRQ[15] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_PHYCTRL_INT[16] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_WIFI_ERROR_TRIG[17] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD_WAKEUP_IRQ[18] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD_ERROR_IRQ[19] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_MUTX_TX_ERR_EVENT[20] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_MUTX_LQ_ERR_EVENT[21] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_TRX_WDT_TRIG[22] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_SPI_FAIL_IND[23] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_PFMU_IBF_TIMER_EXPIRE[24] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_PFMU_IBF_TIMER_RENEW[25] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD1_WAKEUP_IRQ[26] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD1_ERROR_IRQ[27] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD2_WAKEUP_IRQ[28] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD2_ERROR_IRQ[29] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD3_WAKEUP_IRQ[30] - (RW) [DE] BBP control CR
    CR_BAND0_ENA_RDD3_ERROR_IRQ[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD3_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD3_ERROR_IRQ_MASK 0x80000000                // CR_BAND0_ENA_RDD3_ERROR_IRQ[31]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD3_ERROR_IRQ_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD3_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD3_WAKEUP_IRQ_MASK 0x40000000                // CR_BAND0_ENA_RDD3_WAKEUP_IRQ[30]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD3_WAKEUP_IRQ_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD2_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD2_ERROR_IRQ_MASK 0x20000000                // CR_BAND0_ENA_RDD2_ERROR_IRQ[29]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD2_ERROR_IRQ_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD2_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD2_WAKEUP_IRQ_MASK 0x10000000                // CR_BAND0_ENA_RDD2_WAKEUP_IRQ[28]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD2_WAKEUP_IRQ_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD1_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD1_ERROR_IRQ_MASK 0x08000000                // CR_BAND0_ENA_RDD1_ERROR_IRQ[27]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD1_ERROR_IRQ_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD1_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD1_WAKEUP_IRQ_MASK 0x04000000                // CR_BAND0_ENA_RDD1_WAKEUP_IRQ[26]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD1_WAKEUP_IRQ_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PFMU_IBF_TIMER_RENEW_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PFMU_IBF_TIMER_RENEW_MASK 0x02000000                // CR_BAND0_ENA_PFMU_IBF_TIMER_RENEW[25]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PFMU_IBF_TIMER_RENEW_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PFMU_IBF_TIMER_EXPIRE_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PFMU_IBF_TIMER_EXPIRE_MASK 0x01000000                // CR_BAND0_ENA_PFMU_IBF_TIMER_EXPIRE[24]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PFMU_IBF_TIMER_EXPIRE_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_SPI_FAIL_IND_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_SPI_FAIL_IND_MASK 0x00800000                // CR_BAND0_ENA_SPI_FAIL_IND[23]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_SPI_FAIL_IND_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_TRX_WDT_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_TRX_WDT_TRIG_MASK 0x00400000                // CR_BAND0_ENA_TRX_WDT_TRIG[22]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_TRX_WDT_TRIG_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_MUTX_LQ_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_MUTX_LQ_ERR_EVENT_MASK 0x00200000                // CR_BAND0_ENA_MUTX_LQ_ERR_EVENT[21]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_MUTX_LQ_ERR_EVENT_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_MUTX_TX_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_MUTX_TX_ERR_EVENT_MASK 0x00100000                // CR_BAND0_ENA_MUTX_TX_ERR_EVENT[20]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_MUTX_TX_ERR_EVENT_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD_ERROR_IRQ_MASK 0x00080000                // CR_BAND0_ENA_RDD_ERROR_IRQ[19]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD_ERROR_IRQ_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD_WAKEUP_IRQ_MASK 0x00040000                // CR_BAND0_ENA_RDD_WAKEUP_IRQ[18]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_RDD_WAKEUP_IRQ_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_WIFI_ERROR_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_WIFI_ERROR_TRIG_MASK 0x00020000                // CR_BAND0_ENA_WIFI_ERROR_TRIG[17]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_WIFI_ERROR_TRIG_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PHYCTRL_INT_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PHYCTRL_INT_MASK 0x00010000                // CR_BAND0_ENA_PHYCTRL_INT[16]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_ENA_PHYCTRL_INT_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD3_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD3_ERROR_IRQ_MASK 0x00008000                // CR_BAND0_CLR_RDD3_ERROR_IRQ[15]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD3_ERROR_IRQ_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD3_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD3_WAKEUP_IRQ_MASK 0x00004000                // CR_BAND0_CLR_RDD3_WAKEUP_IRQ[14]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD3_WAKEUP_IRQ_SHFT 14
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD2_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD2_ERROR_IRQ_MASK 0x00002000                // CR_BAND0_CLR_RDD2_ERROR_IRQ[13]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD2_ERROR_IRQ_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD2_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD2_WAKEUP_IRQ_MASK 0x00001000                // CR_BAND0_CLR_RDD2_WAKEUP_IRQ[12]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD2_WAKEUP_IRQ_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD1_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD1_ERROR_IRQ_MASK 0x00000800                // CR_BAND0_CLR_RDD1_ERROR_IRQ[11]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD1_ERROR_IRQ_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD1_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD1_WAKEUP_IRQ_MASK 0x00000400                // CR_BAND0_CLR_RDD1_WAKEUP_IRQ[10]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD1_WAKEUP_IRQ_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PFMU_IBF_TIMER_RENEW_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PFMU_IBF_TIMER_RENEW_MASK 0x00000200                // CR_BAND0_CLR_PFMU_IBF_TIMER_RENEW[9]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PFMU_IBF_TIMER_RENEW_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PFMU_IBF_TIMER_EXPIRE_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PFMU_IBF_TIMER_EXPIRE_MASK 0x00000100                // CR_BAND0_CLR_PFMU_IBF_TIMER_EXPIRE[8]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PFMU_IBF_TIMER_EXPIRE_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_SPI_FAIL_IND_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_SPI_FAIL_IND_MASK 0x00000080                // CR_BAND0_CLR_SPI_FAIL_IND[7]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_SPI_FAIL_IND_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_TRX_WDT_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_TRX_WDT_TRIG_MASK 0x00000040                // CR_BAND0_CLR_TRX_WDT_TRIG[6]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_TRX_WDT_TRIG_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_MUTX_LQ_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_MUTX_LQ_ERR_EVENT_MASK 0x00000020                // CR_BAND0_CLR_MUTX_LQ_ERR_EVENT[5]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_MUTX_LQ_ERR_EVENT_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_MUTX_TX_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_MUTX_TX_ERR_EVENT_MASK 0x00000010                // CR_BAND0_CLR_MUTX_TX_ERR_EVENT[4]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_MUTX_TX_ERR_EVENT_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD_ERROR_IRQ_MASK 0x00000008                // CR_BAND0_CLR_RDD_ERROR_IRQ[3]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD_ERROR_IRQ_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD_WAKEUP_IRQ_MASK 0x00000004                // CR_BAND0_CLR_RDD_WAKEUP_IRQ[2]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_RDD_WAKEUP_IRQ_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_WIFI_ERROR_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_WIFI_ERROR_TRIG_MASK 0x00000002                // CR_BAND0_CLR_WIFI_ERROR_TRIG[1]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_WIFI_ERROR_TRIG_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PHYCTRL_INT_ADDR WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PHYCTRL_INT_MASK 0x00000001                // CR_BAND0_CLR_PHYCTRL_INT[0]
#define WF_PHYRX_CTRL_CR_BAND0_MISC_CTRL_CR_BAND0_CLR_PHYCTRL_INT_SHFT 0

/* =====================================================================================

  ---RO_BAND0_MISC_IRQ_STA (0x82000000 + 0x020C)---

    RO_BAND0_IRQ_STA[31..0]      - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_MISC_IRQ_STA_RO_BAND0_IRQ_STA_ADDR WF_PHYRX_CTRL_RO_BAND0_MISC_IRQ_STA_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_MISC_IRQ_STA_RO_BAND0_IRQ_STA_MASK 0xFFFFFFFF                // RO_BAND0_IRQ_STA[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_MISC_IRQ_STA_RO_BAND0_IRQ_STA_SHFT 0

/* =====================================================================================

  ---CR_BAND0_TRX_WDT_RST_MASK (0x82000000 + 0x0210)---

    CR_BAND0_TRX_WDT_RST_MASK[31..0] - (RW) 1: Reset

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_TRX_WDT_RST_MASK_CR_BAND0_TRX_WDT_RST_MASK_ADDR WF_PHYRX_CTRL_CR_BAND0_TRX_WDT_RST_MASK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_TRX_WDT_RST_MASK_CR_BAND0_TRX_WDT_RST_MASK_MASK 0xFFFFFFFF                // CR_BAND0_TRX_WDT_RST_MASK[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_TRX_WDT_RST_MASK_CR_BAND0_TRX_WDT_RST_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_RST_TXFE_CTRL (0x82000000 + 0x0214)---

    CR_WF0_TXFE_RST_DLY_FALL[7..0] - (RW) [DE] BBP control CR
    CR_WF0_TXFE_RST_DLY_RISE[15..8] - (RW) [DE] BBP control CR
    CR_WF1_TXFE_RST_DLY_FALL[23..16] - (RW) [DE] BBP control CR
    CR_WF1_TXFE_RST_DLY_RISE[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF1_TXFE_RST_DLY_RISE_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF1_TXFE_RST_DLY_RISE_MASK 0xFF000000                // CR_WF1_TXFE_RST_DLY_RISE[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF1_TXFE_RST_DLY_RISE_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF1_TXFE_RST_DLY_FALL_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF1_TXFE_RST_DLY_FALL_MASK 0x00FF0000                // CR_WF1_TXFE_RST_DLY_FALL[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF1_TXFE_RST_DLY_FALL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF0_TXFE_RST_DLY_RISE_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF0_TXFE_RST_DLY_RISE_MASK 0x0000FF00                // CR_WF0_TXFE_RST_DLY_RISE[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF0_TXFE_RST_DLY_RISE_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF0_TXFE_RST_DLY_FALL_ADDR WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF0_TXFE_RST_DLY_FALL_MASK 0x000000FF                // CR_WF0_TXFE_RST_DLY_FALL[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_RST_TXFE_CTRL_CR_WF0_TXFE_RST_DLY_FALL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_FFT_MANU_CTRL (0x82000000 + 0x0300)---

    CR_BAND0_FFT_MANU_CTRL[31..0] - (RW) [CSD] Band0 FFT manual mode for RXFDIQ calibration

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_FFT_MANU_CTRL_CR_BAND0_FFT_MANU_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_FFT_MANU_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_FFT_MANU_CTRL_CR_BAND0_FFT_MANU_CTRL_MASK 0xFFFFFFFF                // CR_BAND0_FFT_MANU_CTRL[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_FFT_MANU_CTRL_CR_BAND0_FFT_MANU_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_FFT_BUFF_CTRL (0x82000000 + 0x0304)---

    RESERVED0[3..0]              - (RO) Reserved bits
    CR_BAND0_FFT_BUFF_RADDR[11..4] - (RW) [CSD] Band0 FFT buffer manual mode for RXFDIQ calibration
    CR_BAND0_FFT_BUFF_RA_UPD[12] - (RW) [CSD] Band0 FFT buffer manual mode for RXFDIQ calibration
    RESERVED13[14..13]           - (RO) Reserved bits
    CR_BAND0_FFT_BUFF_RD_RLS[15] - (RW) [CSD] Band0 FFT buffer manual mode for RXFDIQ calibration
    RO_BAND0_FFT_BUFF_RATRB[23..16] - (RO) [CSD] Band0 FFT buffer manual mode for RXFDIQ calibration
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_RO_BAND0_FFT_BUFF_RATRB_ADDR WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_RO_BAND0_FFT_BUFF_RATRB_MASK 0x00FF0000                // RO_BAND0_FFT_BUFF_RATRB[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_RO_BAND0_FFT_BUFF_RATRB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RD_RLS_ADDR WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RD_RLS_MASK 0x00008000                // CR_BAND0_FFT_BUFF_RD_RLS[15]
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RD_RLS_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RA_UPD_ADDR WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RA_UPD_MASK 0x00001000                // CR_BAND0_FFT_BUFF_RA_UPD[12]
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RA_UPD_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RADDR_ADDR WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RADDR_MASK 0x00000FF0                // CR_BAND0_FFT_BUFF_RADDR[11..4]
#define WF_PHYRX_CTRL_CR_BAND0_FFT_BUFF_CTRL_CR_BAND0_FFT_BUFF_RADDR_SHFT 4

/* =====================================================================================

  ---RO_BAND0_FFT_BUFF_READ (0x82000000 + 0x0308)---

    RO_BAND0_FFT_BUFF_RDATA[23..0] - (RO) [CSD] Band0 FFT buffer manual mode for RXFDIQ calibration
    RESERVED24[30..24]           - (RO) Reserved bits
    CR_BAND0_FFT_BUFF_RD_UPD[31] - (RS) [CSD] Band0 FFT buffer manual mode for RXFDIQ calibration

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_CR_BAND0_FFT_BUFF_RD_UPD_ADDR WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_CR_BAND0_FFT_BUFF_RD_UPD_MASK 0x80000000                // CR_BAND0_FFT_BUFF_RD_UPD[31]
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_CR_BAND0_FFT_BUFF_RD_UPD_SHFT 31
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_RO_BAND0_FFT_BUFF_RDATA_ADDR WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_RO_BAND0_FFT_BUFF_RDATA_MASK 0x00FFFFFF                // RO_BAND0_FFT_BUFF_RDATA[23..0]
#define WF_PHYRX_CTRL_RO_BAND0_FFT_BUFF_READ_RO_BAND0_FFT_BUFF_RDATA_SHFT 0

/* =====================================================================================

  ---RO_BAND0_FFT_CSD_DBG (0x82000000 + 0x030C)---

    RO_BAND0_FFT_CSD_DBG[12..0]  - (RO) [CSD] Band0 FFT Debug flag
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_FFT_CSD_DBG_RO_BAND0_FFT_CSD_DBG_ADDR WF_PHYRX_CTRL_RO_BAND0_FFT_CSD_DBG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_FFT_CSD_DBG_RO_BAND0_FFT_CSD_DBG_MASK 0x00001FFF                // RO_BAND0_FFT_CSD_DBG[12..0]
#define WF_PHYRX_CTRL_RO_BAND0_FFT_CSD_DBG_RO_BAND0_FFT_CSD_DBG_SHFT 0

/* =====================================================================================

  ---RO_BAND0_STAT_CORE (0x82000000 + 0x0310)---

    RO_BAND0_STAT_CORE[31..0]    - (RO) [DE] Band0 FFT CORE status monitor

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_STAT_CORE_RO_BAND0_STAT_CORE_ADDR WF_PHYRX_CTRL_RO_BAND0_STAT_CORE_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_STAT_CORE_RO_BAND0_STAT_CORE_MASK 0xFFFFFFFF                // RO_BAND0_STAT_CORE[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_STAT_CORE_RO_BAND0_STAT_CORE_SHFT 0

/* =====================================================================================

  ---RO_BAND0_STAT_REQARB (0x82000000 + 0x0314)---

    RO_BAND0_STAT_REQARB[31..0]  - (RO) [DE] Band0 FFT REQARB status monitor

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_STAT_REQARB_RO_BAND0_STAT_REQARB_ADDR WF_PHYRX_CTRL_RO_BAND0_STAT_REQARB_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_STAT_REQARB_RO_BAND0_STAT_REQARB_MASK 0xFFFFFFFF                // RO_BAND0_STAT_REQARB[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_STAT_REQARB_RO_BAND0_STAT_REQARB_SHFT 0

/* =====================================================================================

  ---CR_FFT_MANU_CBW_DBW_CTRL (0x82000000 + 0x0320)---

    CR_FFT_MANU_CBW_DBW_CTRL[31..0] - (RW) [DE] FFT cbw/dbw control manual mode

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_ADDR WF_PHYRX_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_MASK 0xFFFFFFFF                // CR_FFT_MANU_CBW_DBW_CTRL[31..0]
#define WF_PHYRX_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_CR_FFT_MANU_CBW_DBW_CTRL_SHFT 0

/* =====================================================================================

  ---CR_DBGSGD_CTRL (0x82000000 + 0x0400)---

    CR_BAND0_TRIG_SEL_RDD[0]     - (RW) [DE] BBP control CR
    CR_BAND1_TRIG_SEL_RDD[1]     - (RW) [DE] BBP control CR
    CR_BAND0_SGD_SEL[2]          - (RW) [DE] BBP control CR
    CR_BAND1_SGD_SEL[3]          - (RW) [DE] BBP control CR
    CR_SGD_ADC_BAND_SEL[4]       - (RW) [DE] BBP control CR
    CR_SGD_AFIFO_INP_SEL[7..5]   - (RW) [DE] BBP control CR
    CR_SGD_TRIG_CFG[15..8]       - (RW) [DE] BBP control CR
    CR_SGD_TRIG_ENB[16]          - (RW) [DE] BBP control CR
    CR_SGD_TRIG_TST[17]          - (RW) [DE] BBP control CR
    CR_SGD_STOP_ENB[18]          - (RW) [DE] BBP control CR
    CR_SGD_LOG_OEN[19]           - (RW) [DE] BBP control CR
    CR_SGD_SAMP_SHIFT[22..20]    - (RW) [DE] BBP control CR
    CR_SGD_SAMP_PHASE[23]        - (RW) Sampling edge
                                     0: Positive
                                     1: Negative
    CR_SGD_SAMP_RATE[25..24]     - (RW) Sampling at
                                     0: 20M
                                     1: 40M
                                     2: 80M
                                     3: 160M
    CR_SGD_SAMP_ENB[26]          - (RW) [DE] BBP control CR
    CR_SGD_TEST_MODE[27]         - (RW) [DE] BBP control CR
    CR_SGD_PKT_RST_EN[28]        - (RW) [DE] BBP control CR
    CR_SGD_RESET[29]             - (RW) [DE] BBP control CR
    CR_SGD_VLD_40M[30]           - (RW) [DE] BBP control CR
    CR_SGD_VLD_TOGGLE[31]        - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_VLD_TOGGLE_ADDR    WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_VLD_TOGGLE_MASK    0x80000000                // CR_SGD_VLD_TOGGLE[31]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_VLD_TOGGLE_SHFT    31
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_VLD_40M_ADDR       WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_VLD_40M_MASK       0x40000000                // CR_SGD_VLD_40M[30]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_VLD_40M_SHFT       30
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_RESET_ADDR         WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_RESET_MASK         0x20000000                // CR_SGD_RESET[29]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_RESET_SHFT         29
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_PKT_RST_EN_ADDR    WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_PKT_RST_EN_MASK    0x10000000                // CR_SGD_PKT_RST_EN[28]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_PKT_RST_EN_SHFT    28
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TEST_MODE_ADDR     WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TEST_MODE_MASK     0x08000000                // CR_SGD_TEST_MODE[27]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TEST_MODE_SHFT     27
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_ENB_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_ENB_MASK      0x04000000                // CR_SGD_SAMP_ENB[26]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_ENB_SHFT      26
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_RATE_ADDR     WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_RATE_MASK     0x03000000                // CR_SGD_SAMP_RATE[25..24]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_RATE_SHFT     24
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_PHASE_ADDR    WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_PHASE_MASK    0x00800000                // CR_SGD_SAMP_PHASE[23]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_PHASE_SHFT    23
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_SHIFT_ADDR    WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_SHIFT_MASK    0x00700000                // CR_SGD_SAMP_SHIFT[22..20]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_SAMP_SHIFT_SHFT    20
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_LOG_OEN_ADDR       WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_LOG_OEN_MASK       0x00080000                // CR_SGD_LOG_OEN[19]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_LOG_OEN_SHFT       19
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_STOP_ENB_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_STOP_ENB_MASK      0x00040000                // CR_SGD_STOP_ENB[18]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_STOP_ENB_SHFT      18
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_TST_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_TST_MASK      0x00020000                // CR_SGD_TRIG_TST[17]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_TST_SHFT      17
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_ENB_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_ENB_MASK      0x00010000                // CR_SGD_TRIG_ENB[16]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_ENB_SHFT      16
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_CFG_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_CFG_MASK      0x0000FF00                // CR_SGD_TRIG_CFG[15..8]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_TRIG_CFG_SHFT      8
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_AFIFO_INP_SEL_ADDR WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_AFIFO_INP_SEL_MASK 0x000000E0                // CR_SGD_AFIFO_INP_SEL[7..5]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_AFIFO_INP_SEL_SHFT 5
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_ADC_BAND_SEL_ADDR  WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_ADC_BAND_SEL_MASK  0x00000010                // CR_SGD_ADC_BAND_SEL[4]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_SGD_ADC_BAND_SEL_SHFT  4
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND1_SGD_SEL_ADDR     WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND1_SGD_SEL_MASK     0x00000008                // CR_BAND1_SGD_SEL[3]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND1_SGD_SEL_SHFT     3
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND0_SGD_SEL_ADDR     WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND0_SGD_SEL_MASK     0x00000004                // CR_BAND0_SGD_SEL[2]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND0_SGD_SEL_SHFT     2
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND1_TRIG_SEL_RDD_ADDR WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND1_TRIG_SEL_RDD_MASK 0x00000002                // CR_BAND1_TRIG_SEL_RDD[1]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND1_TRIG_SEL_RDD_SHFT 1
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND0_TRIG_SEL_RDD_ADDR WF_PHYRX_CTRL_CR_DBGSGD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND0_TRIG_SEL_RDD_MASK 0x00000001                // CR_BAND0_TRIG_SEL_RDD[0]
#define WF_PHYRX_CTRL_CR_DBGSGD_CTRL_CR_BAND0_TRIG_SEL_RDD_SHFT 0

/* =====================================================================================

  ---CR_DBGSGD_MODE (0x82000000 + 0x0404)---

    CR_SGD_MODE[7..0]            - (RW) [DE] BBP control CR
    CR_SGD_TRIG_SEL[9..8]        - (RW) [DE] BBP control CR
    CR_SGD_ALWAYS_VLD[10]        - (RW) [DE] BBP control CR
    CR_SGD_CCK_TOAE_VLD[11]      - (RW) [DE] BBP control CR
    CR_SGD_SPECTRUM_SEL[14..12]  - (RW) [DE] BBP control CR
    CR_SGD_DBG_SEL[22..15]       - (RW) [DE] BBP control CR
    CR_SGD_LSCE_SEL[26..23]      - (RW) [DE] BBP control CR
    CR_SGD_RCVT_TRIG_MODE[27]    - (RW) [DE] BBP control CR
    CR_SGD_PACKED_ADC[28]        - (RW) [DE] BBP control CR
    CR_SGD_BT_TRIG[29]           - (RW) [DE] BBP control CR
    CR_BAND0_RBIST_TRIG_STOP[30] - (RW) [DE] BBP control CR
    CR_BAND1_RBIST_TRIG_STOP[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_BAND1_RBIST_TRIG_STOP_ADDR WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_BAND1_RBIST_TRIG_STOP_MASK 0x80000000                // CR_BAND1_RBIST_TRIG_STOP[31]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_BAND1_RBIST_TRIG_STOP_SHFT 31
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_BAND0_RBIST_TRIG_STOP_ADDR WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_BAND0_RBIST_TRIG_STOP_MASK 0x40000000                // CR_BAND0_RBIST_TRIG_STOP[30]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_BAND0_RBIST_TRIG_STOP_SHFT 30
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_BT_TRIG_ADDR       WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_BT_TRIG_MASK       0x20000000                // CR_SGD_BT_TRIG[29]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_BT_TRIG_SHFT       29
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_PACKED_ADC_ADDR    WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_PACKED_ADC_MASK    0x10000000                // CR_SGD_PACKED_ADC[28]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_PACKED_ADC_SHFT    28
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_RCVT_TRIG_MODE_ADDR WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_RCVT_TRIG_MODE_MASK 0x08000000                // CR_SGD_RCVT_TRIG_MODE[27]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_RCVT_TRIG_MODE_SHFT 27
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_LSCE_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_LSCE_SEL_MASK      0x07800000                // CR_SGD_LSCE_SEL[26..23]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_LSCE_SEL_SHFT      23
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_DBG_SEL_ADDR       WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_DBG_SEL_MASK       0x007F8000                // CR_SGD_DBG_SEL[22..15]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_DBG_SEL_SHFT       15
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_SPECTRUM_SEL_ADDR  WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_SPECTRUM_SEL_MASK  0x00007000                // CR_SGD_SPECTRUM_SEL[14..12]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_SPECTRUM_SEL_SHFT  12
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_CCK_TOAE_VLD_ADDR  WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_CCK_TOAE_VLD_MASK  0x00000800                // CR_SGD_CCK_TOAE_VLD[11]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_CCK_TOAE_VLD_SHFT  11
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_ALWAYS_VLD_ADDR    WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_ALWAYS_VLD_MASK    0x00000400                // CR_SGD_ALWAYS_VLD[10]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_ALWAYS_VLD_SHFT    10
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_TRIG_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_TRIG_SEL_MASK      0x00000300                // CR_SGD_TRIG_SEL[9..8]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_TRIG_SEL_SHFT      8
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_MODE_ADDR          WF_PHYRX_CTRL_CR_DBGSGD_MODE_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_MODE_MASK          0x000000FF                // CR_SGD_MODE[7..0]
#define WF_PHYRX_CTRL_CR_DBGSGD_MODE_CR_SGD_MODE_SHFT          0

/* =====================================================================================

  ---CR_DBGSGD_LYR0_MASK (0x82000000 + 0x0408)---

    CR_SGD_LYR0_MASK[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR0_MASK_CR_SGD_LYR0_MASK_ADDR WF_PHYRX_CTRL_CR_DBGSGD_LYR0_MASK_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR0_MASK_CR_SGD_LYR0_MASK_MASK 0xFFFFFFFF                // CR_SGD_LYR0_MASK[31..0]
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR0_MASK_CR_SGD_LYR0_MASK_SHFT 0

/* =====================================================================================

  ---CR_DBGSGD_LYR1_MASK (0x82000000 + 0x040C)---

    CR_SGD_LYR1_MASK[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR1_MASK_CR_SGD_LYR1_MASK_ADDR WF_PHYRX_CTRL_CR_DBGSGD_LYR1_MASK_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR1_MASK_CR_SGD_LYR1_MASK_MASK 0xFFFFFFFF                // CR_SGD_LYR1_MASK[31..0]
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR1_MASK_CR_SGD_LYR1_MASK_SHFT 0

/* =====================================================================================

  ---CR_DBGSGD_LYR2_MASK (0x82000000 + 0x0410)---

    CR_SGD_LYR2_MASK[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR2_MASK_CR_SGD_LYR2_MASK_ADDR WF_PHYRX_CTRL_CR_DBGSGD_LYR2_MASK_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR2_MASK_CR_SGD_LYR2_MASK_MASK 0xFFFFFFFF                // CR_SGD_LYR2_MASK[31..0]
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR2_MASK_CR_SGD_LYR2_MASK_SHFT 0

/* =====================================================================================

  ---CR_DBGSGD_LYR3_MASK (0x82000000 + 0x0414)---

    CR_SGD_LYR3_MASK[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR3_MASK_CR_SGD_LYR3_MASK_ADDR WF_PHYRX_CTRL_CR_DBGSGD_LYR3_MASK_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR3_MASK_CR_SGD_LYR3_MASK_MASK 0xFFFFFFFF                // CR_SGD_LYR3_MASK[31..0]
#define WF_PHYRX_CTRL_CR_DBGSGD_LYR3_MASK_CR_SGD_LYR3_MASK_SHFT 0

/* =====================================================================================

  ---CR_DBGSGD_INDIVIDUAL_SET (0x82000000 + 0x0418)---

    CR_SGD_INDIVIDUAL_MODE[7..0] - (RW) [DE] BBP control CR
    CR_SGD_INDIVIDUAL_DATA[8]    - (RW) [DE] BBP control CR
    CR_SGD_INDIVIDUAL_VLD[9]     - (RW) [DE] BBP control CR
    CR_SGD_RDD_TRIG_SEL[10]      - (RW) [DE] BBP control CR
    CR_SGD_RSVD[31..11]          - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_RSVD_ADDR WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_RSVD_MASK 0xFFFFF800                // CR_SGD_RSVD[31..11]
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_RSVD_SHFT 11
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_RDD_TRIG_SEL_ADDR WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_RDD_TRIG_SEL_MASK 0x00000400                // CR_SGD_RDD_TRIG_SEL[10]
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_RDD_TRIG_SEL_SHFT 10
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_VLD_ADDR WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_VLD_MASK 0x00000200                // CR_SGD_INDIVIDUAL_VLD[9]
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_VLD_SHFT 9
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_DATA_ADDR WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_DATA_MASK 0x00000100                // CR_SGD_INDIVIDUAL_DATA[8]
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_DATA_SHFT 8
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_MODE_ADDR WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_ADDR
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_MODE_MASK 0x000000FF                // CR_SGD_INDIVIDUAL_MODE[7..0]
#define WF_PHYRX_CTRL_CR_DBGSGD_INDIVIDUAL_SET_CR_SGD_INDIVIDUAL_MODE_SHFT 0

/* =====================================================================================

  ---RO_BAND0_DBGSGD_LYR0_TRIG (0x82000000 + 0x0428)---

    RO_BAND0_SGD_LYR0_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR0_TRIG_RO_BAND0_SGD_LYR0_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR0_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR0_TRIG_RO_BAND0_SGD_LYR0_TRIG_MASK 0xFFFFFFFF                // RO_BAND0_SGD_LYR0_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR0_TRIG_RO_BAND0_SGD_LYR0_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND0_DBGSGD_LYR1_TRIG (0x82000000 + 0x042C)---

    RO_BAND0_SGD_LYR1_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR1_TRIG_RO_BAND0_SGD_LYR1_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR1_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR1_TRIG_RO_BAND0_SGD_LYR1_TRIG_MASK 0xFFFFFFFF                // RO_BAND0_SGD_LYR1_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR1_TRIG_RO_BAND0_SGD_LYR1_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND0_DBGSGD_LYR2_TRIG (0x82000000 + 0x0430)---

    RO_BAND0_SGD_LYR2_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR2_TRIG_RO_BAND0_SGD_LYR2_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR2_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR2_TRIG_RO_BAND0_SGD_LYR2_TRIG_MASK 0xFFFFFFFF                // RO_BAND0_SGD_LYR2_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR2_TRIG_RO_BAND0_SGD_LYR2_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND0_DBGSGD_LYR3_TRIG (0x82000000 + 0x0434)---

    RO_BAND0_SGD_LYR3_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR3_TRIG_RO_BAND0_SGD_LYR3_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR3_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR3_TRIG_RO_BAND0_SGD_LYR3_TRIG_MASK 0xFFFFFFFF                // RO_BAND0_SGD_LYR3_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_LYR3_TRIG_RO_BAND0_SGD_LYR3_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND0_DBGSGD_TRGFSM (0x82000000 + 0x0438)---

    RO_BAND0_SGD_TRGFSM[31..0]   - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_TRGFSM_RO_BAND0_SGD_TRGFSM_ADDR WF_PHYRX_CTRL_RO_BAND0_DBGSGD_TRGFSM_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_TRGFSM_RO_BAND0_SGD_TRGFSM_MASK 0xFFFFFFFF                // RO_BAND0_SGD_TRGFSM[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_DBGSGD_TRGFSM_RO_BAND0_SGD_TRGFSM_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_COMBO (0x82000000 + 0x0500)---

    CR_BN0_TRX_WDT0_COUNT_COMBO[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_COMBO[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_COMBO[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_ENA_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_ENA_COMBO_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_COMBO[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_ENA_COMBO_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_COND_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_COND_COMBO_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_COMBO[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_COND_COMBO_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_COUNT_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_COUNT_COMBO_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_COMBO[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_COMBO_CR_BN0_TRX_WDT0_COUNT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK0_COMBO (0x82000000 + 0x0504)---

    CR_BN0_TRX_WDT0_MASK0_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK0_COMBO_CR_BN0_TRX_WDT0_MASK0_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK0_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK0_COMBO_CR_BN0_TRX_WDT0_MASK0_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT0_MASK0_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK0_COMBO_CR_BN0_TRX_WDT0_MASK0_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK1_COMBO (0x82000000 + 0x0508)---

    CR_BN0_TRX_WDT0_MASK1_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK1_COMBO_CR_BN0_TRX_WDT0_MASK1_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK1_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK1_COMBO_CR_BN0_TRX_WDT0_MASK1_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT0_MASK1_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK1_COMBO_CR_BN0_TRX_WDT0_MASK1_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK2_COMBO (0x82000000 + 0x050C)---

    CR_BN0_TRX_WDT0_MASK2_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK2_COMBO_CR_BN0_TRX_WDT0_MASK2_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK2_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK2_COMBO_CR_BN0_TRX_WDT0_MASK2_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT0_MASK2_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK2_COMBO_CR_BN0_TRX_WDT0_MASK2_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK3_COMBO (0x82000000 + 0x0510)---

    CR_BN0_TRX_WDT0_MASK3_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK3_COMBO_CR_BN0_TRX_WDT0_MASK3_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK3_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK3_COMBO_CR_BN0_TRX_WDT0_MASK3_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT0_MASK3_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK3_COMBO_CR_BN0_TRX_WDT0_MASK3_COMBO_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT0_STAT_COMBO (0x82000000 + 0x0514)---

    RO_BN0_TRX_WDT0_STAT_COMBO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_COMBO_RO_BN0_TRX_WDT0_STAT_COMBO_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_COMBO_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_COMBO_RO_BN0_TRX_WDT0_STAT_COMBO_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT0_STAT_COMBO[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_COMBO_RO_BN0_TRX_WDT0_STAT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_PHYCTRL (0x82000000 + 0x0520)---

    CR_BN0_TRX_WDT0_COUNT_PHYCTRL[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_PHYCTRL[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_PHYCTRL[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_ENA_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_ENA_PHYCTRL_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_PHYCTRL[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_ENA_PHYCTRL_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_COND_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_COND_PHYCTRL_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_PHYCTRL[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_COND_PHYCTRL_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_COUNT_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_COUNT_PHYCTRL_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_PHYCTRL[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_PHYCTRL_CR_BN0_TRX_WDT0_COUNT_PHYCTRL_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_PHYCTRL_L (0x82000000 + 0x0524)---

    CR_BN0_TRX_WDT0_MASK_PHYCTRL_L[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT0_MASK_PHYCTRL_L[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_CR_BN0_TRX_WDT0_MASK_PHYCTRL_L_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_PHYCTRL_H (0x82000000 + 0x0528)---

    CR_BN0_TRX_WDT0_MASK_PHYCTRL_H[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_MASK_PHYCTRL_H[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_CR_BN0_TRX_WDT0_MASK_PHYCTRL_H_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_CAGC (0x82000000 + 0x0530)---

    CR_BN0_TRX_WDT0_COUNT_CAGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_CAGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_CAGC[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_ENA_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_ENA_CAGC_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_CAGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_ENA_CAGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_COND_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_COND_CAGC_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_CAGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_COND_CAGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_COUNT_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_COUNT_CAGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_CAGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_CAGC_CR_BN0_TRX_WDT0_COUNT_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_CAGC (0x82000000 + 0x0534)---

    CR_BN0_TRX_WDT0_MASK_CAGC[11..0] - (RW) [DE] BBP control CR
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_CAGC_CR_BN0_TRX_WDT0_MASK_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_CAGC_CR_BN0_TRX_WDT0_MASK_CAGC_MASK 0x00000FFF                // CR_BN0_TRX_WDT0_MASK_CAGC[11..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_CAGC_CR_BN0_TRX_WDT0_MASK_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_OPOST (0x82000000 + 0x0538)---

    CR_BN0_TRX_WDT0_COUNT_OPOST[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_OPOST[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_OPOST[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_ENA_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_ENA_OPOST_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_OPOST[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_ENA_OPOST_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_COND_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_COND_OPOST_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_OPOST[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_COND_OPOST_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_COUNT_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_COUNT_OPOST_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_OPOST[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_OPOST_CR_BN0_TRX_WDT0_COUNT_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_OPOST (0x82000000 + 0x053C)---

    CR_BN0_TRX_WDT0_MASK_OPOST[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_OPOST_CR_BN0_TRX_WDT0_MASK_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_OPOST_CR_BN0_TRX_WDT0_MASK_OPOST_MASK 0x000003FF                // CR_BN0_TRX_WDT0_MASK_OPOST[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_OPOST_CR_BN0_TRX_WDT0_MASK_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_FFT (0x82000000 + 0x0540)---

    CR_BN0_TRX_WDT0_COUNT_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_FFT[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_FFT[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_ENA_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_ENA_FFT_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_FFT[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_ENA_FFT_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_COND_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_COND_FFT_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_FFT[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_COND_FFT_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_COUNT_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_COUNT_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_FFT_CR_BN0_TRX_WDT0_COUNT_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_FFT (0x82000000 + 0x0544)---

    CR_BN0_TRX_WDT0_MASK_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_FFT_CR_BN0_TRX_WDT0_MASK_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_FFT_CR_BN0_TRX_WDT0_MASK_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_MASK_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_FFT_CR_BN0_TRX_WDT0_MASK_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_RXTD (0x82000000 + 0x0548)---

    CR_BN0_TRX_WDT0_COUNT_RXTD[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_RXTD[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_RXTD[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_ENA_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_ENA_RXTD_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_RXTD[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_ENA_RXTD_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_COND_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_COND_RXTD_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_RXTD[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_COND_RXTD_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_COUNT_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_COUNT_RXTD_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_RXTD[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXTD_CR_BN0_TRX_WDT0_COUNT_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_RXTD (0x82000000 + 0x054C)---

    CR_BN0_TRX_WDT0_MASK_RXTD[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXTD_CR_BN0_TRX_WDT0_MASK_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXTD_CR_BN0_TRX_WDT0_MASK_RXTD_MASK 0x000003FF                // CR_BN0_TRX_WDT0_MASK_RXTD[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXTD_CR_BN0_TRX_WDT0_MASK_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_AGC (0x82000000 + 0x0550)---

    CR_BN0_TRX_WDT0_COUNT_AGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_AGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_AGC[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_ENA_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_ENA_AGC_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_AGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_ENA_AGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_COND_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_COND_AGC_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_AGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_COND_AGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_COUNT_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_COUNT_AGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_AGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_AGC_CR_BN0_TRX_WDT0_COUNT_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_AGC (0x82000000 + 0x0554)---

    CR_BN0_TRX_WDT0_MASK_AGC[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_AGC_CR_BN0_TRX_WDT0_MASK_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_AGC_CR_BN0_TRX_WDT0_MASK_AGC_MASK 0x000003FF                // CR_BN0_TRX_WDT0_MASK_AGC[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_AGC_CR_BN0_TRX_WDT0_MASK_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_CTRL_RXFE (0x82000000 + 0x0558)---

    CR_BN0_TRX_WDT0_COUNT_RXFE[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT0_COND_RXFE[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT0_ENA_RXFE[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_ENA_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_ENA_RXFE_MASK 0x80000000                // CR_BN0_TRX_WDT0_ENA_RXFE[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_ENA_RXFE_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_COND_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_COND_RXFE_MASK 0x40000000                // CR_BN0_TRX_WDT0_COND_RXFE[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_COND_RXFE_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_COUNT_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_COUNT_RXFE_MASK 0x0000FFFF                // CR_BN0_TRX_WDT0_COUNT_RXFE[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_CTRL_RXFE_CR_BN0_TRX_WDT0_COUNT_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_MASK_RXFE (0x82000000 + 0x055C)---

    CR_BN0_TRX_WDT0_MASK_RXFE[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXFE_CR_BN0_TRX_WDT0_MASK_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXFE_CR_BN0_TRX_WDT0_MASK_RXFE_MASK 0x000003FF                // CR_BN0_TRX_WDT0_MASK_RXFE[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_MASK_RXFE_CR_BN0_TRX_WDT0_MASK_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT0_STAT_CTRL (0x82000000 + 0x0560)---

    CR_BN0_TRX_WDT0_STAT_SELECT[2..0] - (RW) [DE] BBP control CR
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_STAT_CTRL_CR_BN0_TRX_WDT0_STAT_SELECT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_STAT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_STAT_CTRL_CR_BN0_TRX_WDT0_STAT_SELECT_MASK 0x00000007                // CR_BN0_TRX_WDT0_STAT_SELECT[2..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT0_STAT_CTRL_CR_BN0_TRX_WDT0_STAT_SELECT_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT0_STAT_FUNIT (0x82000000 + 0x0564)---

    RO_BN0_TRX_WDT0_STAT_FUNIT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_FUNIT_RO_BN0_TRX_WDT0_STAT_FUNIT_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_FUNIT_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_FUNIT_RO_BN0_TRX_WDT0_STAT_FUNIT_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT0_STAT_FUNIT[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT0_STAT_FUNIT_RO_BN0_TRX_WDT0_STAT_FUNIT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_COMBO (0x82000000 + 0x0580)---

    CR_BN0_TRX_WDT1_COUNT_COMBO[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_COMBO[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_COMBO[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_ENA_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_ENA_COMBO_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_COMBO[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_ENA_COMBO_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_COND_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_COND_COMBO_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_COMBO[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_COND_COMBO_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_COUNT_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_COUNT_COMBO_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_COMBO[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_COMBO_CR_BN0_TRX_WDT1_COUNT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK0_COMBO (0x82000000 + 0x0584)---

    CR_BN0_TRX_WDT1_MASK0_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK0_COMBO_CR_BN0_TRX_WDT1_MASK0_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK0_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK0_COMBO_CR_BN0_TRX_WDT1_MASK0_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT1_MASK0_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK0_COMBO_CR_BN0_TRX_WDT1_MASK0_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK1_COMBO (0x82000000 + 0x0588)---

    CR_BN0_TRX_WDT1_MASK1_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK1_COMBO_CR_BN0_TRX_WDT1_MASK1_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK1_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK1_COMBO_CR_BN0_TRX_WDT1_MASK1_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT1_MASK1_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK1_COMBO_CR_BN0_TRX_WDT1_MASK1_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK2_COMBO (0x82000000 + 0x058C)---

    CR_BN0_TRX_WDT1_MASK2_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK2_COMBO_CR_BN0_TRX_WDT1_MASK2_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK2_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK2_COMBO_CR_BN0_TRX_WDT1_MASK2_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT1_MASK2_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK2_COMBO_CR_BN0_TRX_WDT1_MASK2_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK3_COMBO (0x82000000 + 0x0590)---

    CR_BN0_TRX_WDT1_MASK3_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK3_COMBO_CR_BN0_TRX_WDT1_MASK3_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK3_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK3_COMBO_CR_BN0_TRX_WDT1_MASK3_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT1_MASK3_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK3_COMBO_CR_BN0_TRX_WDT1_MASK3_COMBO_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT1_STAT_COMBO (0x82000000 + 0x0594)---

    RO_BN0_TRX_WDT1_STAT_COMBO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_COMBO_RO_BN0_TRX_WDT1_STAT_COMBO_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_COMBO_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_COMBO_RO_BN0_TRX_WDT1_STAT_COMBO_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT1_STAT_COMBO[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_COMBO_RO_BN0_TRX_WDT1_STAT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_PHYCTRL (0x82000000 + 0x05A0)---

    CR_BN0_TRX_WDT1_COUNT_PHYCTRL[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_PHYCTRL[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_PHYCTRL[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_ENA_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_ENA_PHYCTRL_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_PHYCTRL[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_ENA_PHYCTRL_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_COND_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_COND_PHYCTRL_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_PHYCTRL[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_COND_PHYCTRL_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_COUNT_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_COUNT_PHYCTRL_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_PHYCTRL[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_PHYCTRL_CR_BN0_TRX_WDT1_COUNT_PHYCTRL_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_PHYCTRL_L (0x82000000 + 0x05A4)---

    CR_BN0_TRX_WDT1_MASK_PHYCTRL_L[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT1_MASK_PHYCTRL_L[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_CR_BN0_TRX_WDT1_MASK_PHYCTRL_L_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_PHYCTRL_H (0x82000000 + 0x05A8)---

    CR_BN0_TRX_WDT1_MASK_PHYCTRL_H[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_MASK_PHYCTRL_H[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_CR_BN0_TRX_WDT1_MASK_PHYCTRL_H_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_CAGC (0x82000000 + 0x05B0)---

    CR_BN0_TRX_WDT1_COUNT_CAGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_CAGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_CAGC[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_ENA_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_ENA_CAGC_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_CAGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_ENA_CAGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_COND_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_COND_CAGC_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_CAGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_COND_CAGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_COUNT_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_COUNT_CAGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_CAGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_CAGC_CR_BN0_TRX_WDT1_COUNT_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_CAGC (0x82000000 + 0x05B4)---

    CR_BN0_TRX_WDT1_MASK_CAGC[11..0] - (RW) [DE] BBP control CR
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_CAGC_CR_BN0_TRX_WDT1_MASK_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_CAGC_CR_BN0_TRX_WDT1_MASK_CAGC_MASK 0x00000FFF                // CR_BN0_TRX_WDT1_MASK_CAGC[11..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_CAGC_CR_BN0_TRX_WDT1_MASK_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_OPOST (0x82000000 + 0x05B8)---

    CR_BN0_TRX_WDT1_COUNT_OPOST[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_OPOST[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_OPOST[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_ENA_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_ENA_OPOST_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_OPOST[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_ENA_OPOST_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_COND_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_COND_OPOST_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_OPOST[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_COND_OPOST_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_COUNT_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_COUNT_OPOST_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_OPOST[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_OPOST_CR_BN0_TRX_WDT1_COUNT_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_OPOST (0x82000000 + 0x05BC)---

    CR_BN0_TRX_WDT1_MASK_OPOST[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_OPOST_CR_BN0_TRX_WDT1_MASK_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_OPOST_CR_BN0_TRX_WDT1_MASK_OPOST_MASK 0x000003FF                // CR_BN0_TRX_WDT1_MASK_OPOST[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_OPOST_CR_BN0_TRX_WDT1_MASK_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_FFT (0x82000000 + 0x05C0)---

    CR_BN0_TRX_WDT1_COUNT_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_FFT[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_FFT[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_ENA_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_ENA_FFT_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_FFT[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_ENA_FFT_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_COND_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_COND_FFT_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_FFT[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_COND_FFT_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_COUNT_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_COUNT_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_FFT_CR_BN0_TRX_WDT1_COUNT_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_FFT (0x82000000 + 0x05C4)---

    CR_BN0_TRX_WDT1_MASK_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_FFT_CR_BN0_TRX_WDT1_MASK_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_FFT_CR_BN0_TRX_WDT1_MASK_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_MASK_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_FFT_CR_BN0_TRX_WDT1_MASK_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_RXTD (0x82000000 + 0x05C8)---

    CR_BN0_TRX_WDT1_COUNT_RXTD[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_RXTD[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_RXTD[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_ENA_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_ENA_RXTD_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_RXTD[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_ENA_RXTD_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_COND_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_COND_RXTD_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_RXTD[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_COND_RXTD_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_COUNT_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_COUNT_RXTD_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_RXTD[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXTD_CR_BN0_TRX_WDT1_COUNT_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_RXTD (0x82000000 + 0x05CC)---

    CR_BN0_TRX_WDT1_MASK_RXTD[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXTD_CR_BN0_TRX_WDT1_MASK_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXTD_CR_BN0_TRX_WDT1_MASK_RXTD_MASK 0x000003FF                // CR_BN0_TRX_WDT1_MASK_RXTD[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXTD_CR_BN0_TRX_WDT1_MASK_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_AGC (0x82000000 + 0x05D0)---

    CR_BN0_TRX_WDT1_COUNT_AGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_AGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_AGC[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_ENA_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_ENA_AGC_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_AGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_ENA_AGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_COND_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_COND_AGC_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_AGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_COND_AGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_COUNT_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_COUNT_AGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_AGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_AGC_CR_BN0_TRX_WDT1_COUNT_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_AGC (0x82000000 + 0x05D4)---

    CR_BN0_TRX_WDT1_MASK_AGC[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_AGC_CR_BN0_TRX_WDT1_MASK_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_AGC_CR_BN0_TRX_WDT1_MASK_AGC_MASK 0x000003FF                // CR_BN0_TRX_WDT1_MASK_AGC[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_AGC_CR_BN0_TRX_WDT1_MASK_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_CTRL_RXFE (0x82000000 + 0x05D8)---

    CR_BN0_TRX_WDT1_COUNT_RXFE[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT1_COND_RXFE[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT1_ENA_RXFE[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_ENA_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_ENA_RXFE_MASK 0x80000000                // CR_BN0_TRX_WDT1_ENA_RXFE[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_ENA_RXFE_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_COND_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_COND_RXFE_MASK 0x40000000                // CR_BN0_TRX_WDT1_COND_RXFE[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_COND_RXFE_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_COUNT_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_COUNT_RXFE_MASK 0x0000FFFF                // CR_BN0_TRX_WDT1_COUNT_RXFE[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_CTRL_RXFE_CR_BN0_TRX_WDT1_COUNT_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_MASK_RXFE (0x82000000 + 0x05DC)---

    CR_BN0_TRX_WDT1_MASK_RXFE[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXFE_CR_BN0_TRX_WDT1_MASK_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXFE_CR_BN0_TRX_WDT1_MASK_RXFE_MASK 0x000003FF                // CR_BN0_TRX_WDT1_MASK_RXFE[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_MASK_RXFE_CR_BN0_TRX_WDT1_MASK_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT1_STAT_CTRL (0x82000000 + 0x05E0)---

    CR_BN0_TRX_WDT1_STAT_SELECT[2..0] - (RW) [DE] BBP control CR
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_STAT_CTRL_CR_BN0_TRX_WDT1_STAT_SELECT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_STAT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_STAT_CTRL_CR_BN0_TRX_WDT1_STAT_SELECT_MASK 0x00000007                // CR_BN0_TRX_WDT1_STAT_SELECT[2..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT1_STAT_CTRL_CR_BN0_TRX_WDT1_STAT_SELECT_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT1_STAT_FUNIT (0x82000000 + 0x05E4)---

    RO_BN0_TRX_WDT1_STAT_FUNIT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_FUNIT_RO_BN0_TRX_WDT1_STAT_FUNIT_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_FUNIT_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_FUNIT_RO_BN0_TRX_WDT1_STAT_FUNIT_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT1_STAT_FUNIT[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT1_STAT_FUNIT_RO_BN0_TRX_WDT1_STAT_FUNIT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_COMBO (0x82000000 + 0x0600)---

    CR_BN0_TRX_WDT2_COUNT_COMBO[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_COMBO[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_COMBO[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_ENA_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_ENA_COMBO_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_COMBO[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_ENA_COMBO_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_COND_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_COND_COMBO_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_COMBO[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_COND_COMBO_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_COUNT_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_COUNT_COMBO_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_COMBO[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_COMBO_CR_BN0_TRX_WDT2_COUNT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK0_COMBO (0x82000000 + 0x0604)---

    CR_BN0_TRX_WDT2_MASK0_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK0_COMBO_CR_BN0_TRX_WDT2_MASK0_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK0_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK0_COMBO_CR_BN0_TRX_WDT2_MASK0_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT2_MASK0_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK0_COMBO_CR_BN0_TRX_WDT2_MASK0_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK1_COMBO (0x82000000 + 0x0608)---

    CR_BN0_TRX_WDT2_MASK1_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK1_COMBO_CR_BN0_TRX_WDT2_MASK1_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK1_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK1_COMBO_CR_BN0_TRX_WDT2_MASK1_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT2_MASK1_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK1_COMBO_CR_BN0_TRX_WDT2_MASK1_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK2_COMBO (0x82000000 + 0x060C)---

    CR_BN0_TRX_WDT2_MASK2_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK2_COMBO_CR_BN0_TRX_WDT2_MASK2_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK2_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK2_COMBO_CR_BN0_TRX_WDT2_MASK2_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT2_MASK2_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK2_COMBO_CR_BN0_TRX_WDT2_MASK2_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK3_COMBO (0x82000000 + 0x0610)---

    CR_BN0_TRX_WDT2_MASK3_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK3_COMBO_CR_BN0_TRX_WDT2_MASK3_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK3_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK3_COMBO_CR_BN0_TRX_WDT2_MASK3_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT2_MASK3_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK3_COMBO_CR_BN0_TRX_WDT2_MASK3_COMBO_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT2_STAT_COMBO (0x82000000 + 0x0614)---

    RO_BN0_TRX_WDT2_STAT_COMBO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_COMBO_RO_BN0_TRX_WDT2_STAT_COMBO_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_COMBO_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_COMBO_RO_BN0_TRX_WDT2_STAT_COMBO_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT2_STAT_COMBO[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_COMBO_RO_BN0_TRX_WDT2_STAT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_PHYCTRL (0x82000000 + 0x0620)---

    CR_BN0_TRX_WDT2_COUNT_PHYCTRL[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_PHYCTRL[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_PHYCTRL[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_ENA_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_ENA_PHYCTRL_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_PHYCTRL[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_ENA_PHYCTRL_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_COND_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_COND_PHYCTRL_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_PHYCTRL[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_COND_PHYCTRL_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_COUNT_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_COUNT_PHYCTRL_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_PHYCTRL[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_PHYCTRL_CR_BN0_TRX_WDT2_COUNT_PHYCTRL_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_PHYCTRL_L (0x82000000 + 0x0624)---

    CR_BN0_TRX_WDT2_MASK_PHYCTRL_L[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT2_MASK_PHYCTRL_L[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_CR_BN0_TRX_WDT2_MASK_PHYCTRL_L_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_PHYCTRL_H (0x82000000 + 0x0628)---

    CR_BN0_TRX_WDT2_MASK_PHYCTRL_H[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_MASK_PHYCTRL_H[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_CR_BN0_TRX_WDT2_MASK_PHYCTRL_H_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_CAGC (0x82000000 + 0x0630)---

    CR_BN0_TRX_WDT2_COUNT_CAGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_CAGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_CAGC[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_ENA_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_ENA_CAGC_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_CAGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_ENA_CAGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_COND_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_COND_CAGC_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_CAGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_COND_CAGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_COUNT_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_COUNT_CAGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_CAGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_CAGC_CR_BN0_TRX_WDT2_COUNT_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_CAGC (0x82000000 + 0x0634)---

    CR_BN0_TRX_WDT2_MASK_CAGC[11..0] - (RW) [DE] BBP control CR
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_CAGC_CR_BN0_TRX_WDT2_MASK_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_CAGC_CR_BN0_TRX_WDT2_MASK_CAGC_MASK 0x00000FFF                // CR_BN0_TRX_WDT2_MASK_CAGC[11..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_CAGC_CR_BN0_TRX_WDT2_MASK_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_OPOST (0x82000000 + 0x0638)---

    CR_BN0_TRX_WDT2_COUNT_OPOST[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_OPOST[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_OPOST[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_ENA_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_ENA_OPOST_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_OPOST[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_ENA_OPOST_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_COND_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_COND_OPOST_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_OPOST[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_COND_OPOST_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_COUNT_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_COUNT_OPOST_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_OPOST[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_OPOST_CR_BN0_TRX_WDT2_COUNT_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_OPOST (0x82000000 + 0x063C)---

    CR_BN0_TRX_WDT2_MASK_OPOST[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_OPOST_CR_BN0_TRX_WDT2_MASK_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_OPOST_CR_BN0_TRX_WDT2_MASK_OPOST_MASK 0x000003FF                // CR_BN0_TRX_WDT2_MASK_OPOST[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_OPOST_CR_BN0_TRX_WDT2_MASK_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_FFT (0x82000000 + 0x0640)---

    CR_BN0_TRX_WDT2_COUNT_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_FFT[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_FFT[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_ENA_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_ENA_FFT_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_FFT[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_ENA_FFT_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_COND_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_COND_FFT_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_FFT[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_COND_FFT_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_COUNT_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_COUNT_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_FFT_CR_BN0_TRX_WDT2_COUNT_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_FFT (0x82000000 + 0x0644)---

    CR_BN0_TRX_WDT2_MASK_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_FFT_CR_BN0_TRX_WDT2_MASK_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_FFT_CR_BN0_TRX_WDT2_MASK_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_MASK_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_FFT_CR_BN0_TRX_WDT2_MASK_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_RXTD (0x82000000 + 0x0648)---

    CR_BN0_TRX_WDT2_COUNT_RXTD[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_RXTD[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_RXTD[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_ENA_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_ENA_RXTD_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_RXTD[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_ENA_RXTD_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_COND_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_COND_RXTD_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_RXTD[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_COND_RXTD_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_COUNT_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_COUNT_RXTD_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_RXTD[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXTD_CR_BN0_TRX_WDT2_COUNT_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_RXTD (0x82000000 + 0x064C)---

    CR_BN0_TRX_WDT2_MASK_RXTD[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXTD_CR_BN0_TRX_WDT2_MASK_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXTD_CR_BN0_TRX_WDT2_MASK_RXTD_MASK 0x000003FF                // CR_BN0_TRX_WDT2_MASK_RXTD[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXTD_CR_BN0_TRX_WDT2_MASK_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_AGC (0x82000000 + 0x0650)---

    CR_BN0_TRX_WDT2_COUNT_AGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_AGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_AGC[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_ENA_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_ENA_AGC_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_AGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_ENA_AGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_COND_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_COND_AGC_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_AGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_COND_AGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_COUNT_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_COUNT_AGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_AGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_AGC_CR_BN0_TRX_WDT2_COUNT_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_AGC (0x82000000 + 0x0654)---

    CR_BN0_TRX_WDT2_MASK_AGC[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_AGC_CR_BN0_TRX_WDT2_MASK_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_AGC_CR_BN0_TRX_WDT2_MASK_AGC_MASK 0x000003FF                // CR_BN0_TRX_WDT2_MASK_AGC[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_AGC_CR_BN0_TRX_WDT2_MASK_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_CTRL_RXFE (0x82000000 + 0x0658)---

    CR_BN0_TRX_WDT2_COUNT_RXFE[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT2_COND_RXFE[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT2_ENA_RXFE[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_ENA_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_ENA_RXFE_MASK 0x80000000                // CR_BN0_TRX_WDT2_ENA_RXFE[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_ENA_RXFE_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_COND_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_COND_RXFE_MASK 0x40000000                // CR_BN0_TRX_WDT2_COND_RXFE[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_COND_RXFE_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_COUNT_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_COUNT_RXFE_MASK 0x0000FFFF                // CR_BN0_TRX_WDT2_COUNT_RXFE[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_CTRL_RXFE_CR_BN0_TRX_WDT2_COUNT_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_MASK_RXFE (0x82000000 + 0x065C)---

    CR_BN0_TRX_WDT2_MASK_RXFE[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXFE_CR_BN0_TRX_WDT2_MASK_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXFE_CR_BN0_TRX_WDT2_MASK_RXFE_MASK 0x000003FF                // CR_BN0_TRX_WDT2_MASK_RXFE[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_MASK_RXFE_CR_BN0_TRX_WDT2_MASK_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT2_STAT_CTRL (0x82000000 + 0x0660)---

    CR_BN0_TRX_WDT2_STAT_SELECT[2..0] - (RW) [DE] BBP control CR
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_STAT_CTRL_CR_BN0_TRX_WDT2_STAT_SELECT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_STAT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_STAT_CTRL_CR_BN0_TRX_WDT2_STAT_SELECT_MASK 0x00000007                // CR_BN0_TRX_WDT2_STAT_SELECT[2..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT2_STAT_CTRL_CR_BN0_TRX_WDT2_STAT_SELECT_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT2_STAT_FUNIT (0x82000000 + 0x0664)---

    RO_BN0_TRX_WDT2_STAT_FUNIT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_FUNIT_RO_BN0_TRX_WDT2_STAT_FUNIT_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_FUNIT_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_FUNIT_RO_BN0_TRX_WDT2_STAT_FUNIT_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT2_STAT_FUNIT[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT2_STAT_FUNIT_RO_BN0_TRX_WDT2_STAT_FUNIT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_COMBO (0x82000000 + 0x0680)---

    CR_BN0_TRX_WDT3_COUNT_COMBO[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_COMBO[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_COMBO[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_ENA_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_ENA_COMBO_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_COMBO[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_ENA_COMBO_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_COND_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_COND_COMBO_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_COMBO[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_COND_COMBO_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_COUNT_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_COUNT_COMBO_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_COMBO[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_COMBO_CR_BN0_TRX_WDT3_COUNT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK0_COMBO (0x82000000 + 0x0684)---

    CR_BN0_TRX_WDT3_MASK0_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK0_COMBO_CR_BN0_TRX_WDT3_MASK0_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK0_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK0_COMBO_CR_BN0_TRX_WDT3_MASK0_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT3_MASK0_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK0_COMBO_CR_BN0_TRX_WDT3_MASK0_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK1_COMBO (0x82000000 + 0x0688)---

    CR_BN0_TRX_WDT3_MASK1_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK1_COMBO_CR_BN0_TRX_WDT3_MASK1_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK1_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK1_COMBO_CR_BN0_TRX_WDT3_MASK1_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT3_MASK1_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK1_COMBO_CR_BN0_TRX_WDT3_MASK1_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK2_COMBO (0x82000000 + 0x068C)---

    CR_BN0_TRX_WDT3_MASK2_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK2_COMBO_CR_BN0_TRX_WDT3_MASK2_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK2_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK2_COMBO_CR_BN0_TRX_WDT3_MASK2_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT3_MASK2_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK2_COMBO_CR_BN0_TRX_WDT3_MASK2_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK3_COMBO (0x82000000 + 0x0690)---

    CR_BN0_TRX_WDT3_MASK3_COMBO[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK3_COMBO_CR_BN0_TRX_WDT3_MASK3_COMBO_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK3_COMBO_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK3_COMBO_CR_BN0_TRX_WDT3_MASK3_COMBO_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT3_MASK3_COMBO[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK3_COMBO_CR_BN0_TRX_WDT3_MASK3_COMBO_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT3_STAT_COMBO (0x82000000 + 0x0694)---

    RO_BN0_TRX_WDT3_STAT_COMBO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_COMBO_RO_BN0_TRX_WDT3_STAT_COMBO_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_COMBO_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_COMBO_RO_BN0_TRX_WDT3_STAT_COMBO_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT3_STAT_COMBO[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_COMBO_RO_BN0_TRX_WDT3_STAT_COMBO_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_PHYCTRL (0x82000000 + 0x06A0)---

    CR_BN0_TRX_WDT3_COUNT_PHYCTRL[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_PHYCTRL[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_PHYCTRL[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_ENA_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_ENA_PHYCTRL_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_PHYCTRL[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_ENA_PHYCTRL_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_COND_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_COND_PHYCTRL_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_PHYCTRL[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_COND_PHYCTRL_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_COUNT_PHYCTRL_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_COUNT_PHYCTRL_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_PHYCTRL[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_PHYCTRL_CR_BN0_TRX_WDT3_COUNT_PHYCTRL_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_PHYCTRL_L (0x82000000 + 0x06A4)---

    CR_BN0_TRX_WDT3_MASK_PHYCTRL_L[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_MASK 0xFFFFFFFF                // CR_BN0_TRX_WDT3_MASK_PHYCTRL_L[31..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_CR_BN0_TRX_WDT3_MASK_PHYCTRL_L_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_PHYCTRL_H (0x82000000 + 0x06A8)---

    CR_BN0_TRX_WDT3_MASK_PHYCTRL_H[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_MASK_PHYCTRL_H[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_CR_BN0_TRX_WDT3_MASK_PHYCTRL_H_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_CAGC (0x82000000 + 0x06B0)---

    CR_BN0_TRX_WDT3_COUNT_CAGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_CAGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_CAGC[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_ENA_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_ENA_CAGC_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_CAGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_ENA_CAGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_COND_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_COND_CAGC_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_CAGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_COND_CAGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_COUNT_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_COUNT_CAGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_CAGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_CAGC_CR_BN0_TRX_WDT3_COUNT_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_CAGC (0x82000000 + 0x06B4)---

    CR_BN0_TRX_WDT3_MASK_CAGC[11..0] - (RW) [DE] BBP control CR
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_CAGC_CR_BN0_TRX_WDT3_MASK_CAGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_CAGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_CAGC_CR_BN0_TRX_WDT3_MASK_CAGC_MASK 0x00000FFF                // CR_BN0_TRX_WDT3_MASK_CAGC[11..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_CAGC_CR_BN0_TRX_WDT3_MASK_CAGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_OPOST (0x82000000 + 0x06B8)---

    CR_BN0_TRX_WDT3_COUNT_OPOST[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_OPOST[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_OPOST[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_ENA_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_ENA_OPOST_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_OPOST[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_ENA_OPOST_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_COND_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_COND_OPOST_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_OPOST[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_COND_OPOST_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_COUNT_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_COUNT_OPOST_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_OPOST[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_OPOST_CR_BN0_TRX_WDT3_COUNT_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_OPOST (0x82000000 + 0x06BC)---

    CR_BN0_TRX_WDT3_MASK_OPOST[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_OPOST_CR_BN0_TRX_WDT3_MASK_OPOST_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_OPOST_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_OPOST_CR_BN0_TRX_WDT3_MASK_OPOST_MASK 0x000003FF                // CR_BN0_TRX_WDT3_MASK_OPOST[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_OPOST_CR_BN0_TRX_WDT3_MASK_OPOST_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_FFT (0x82000000 + 0x06C0)---

    CR_BN0_TRX_WDT3_COUNT_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_FFT[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_FFT[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_ENA_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_ENA_FFT_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_FFT[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_ENA_FFT_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_COND_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_COND_FFT_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_FFT[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_COND_FFT_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_COUNT_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_COUNT_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_FFT_CR_BN0_TRX_WDT3_COUNT_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_FFT (0x82000000 + 0x06C4)---

    CR_BN0_TRX_WDT3_MASK_FFT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_FFT_CR_BN0_TRX_WDT3_MASK_FFT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_FFT_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_FFT_CR_BN0_TRX_WDT3_MASK_FFT_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_MASK_FFT[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_FFT_CR_BN0_TRX_WDT3_MASK_FFT_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_RXTD (0x82000000 + 0x06C8)---

    CR_BN0_TRX_WDT3_COUNT_RXTD[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_RXTD[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_RXTD[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_ENA_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_ENA_RXTD_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_RXTD[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_ENA_RXTD_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_COND_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_COND_RXTD_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_RXTD[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_COND_RXTD_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_COUNT_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_COUNT_RXTD_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_RXTD[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXTD_CR_BN0_TRX_WDT3_COUNT_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_RXTD (0x82000000 + 0x06CC)---

    CR_BN0_TRX_WDT3_MASK_RXTD[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXTD_CR_BN0_TRX_WDT3_MASK_RXTD_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXTD_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXTD_CR_BN0_TRX_WDT3_MASK_RXTD_MASK 0x000003FF                // CR_BN0_TRX_WDT3_MASK_RXTD[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXTD_CR_BN0_TRX_WDT3_MASK_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_AGC (0x82000000 + 0x06D0)---

    CR_BN0_TRX_WDT3_COUNT_AGC[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_AGC[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_AGC[31]  - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_ENA_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_ENA_AGC_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_AGC[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_ENA_AGC_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_COND_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_COND_AGC_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_AGC[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_COND_AGC_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_COUNT_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_COUNT_AGC_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_AGC[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_AGC_CR_BN0_TRX_WDT3_COUNT_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_AGC (0x82000000 + 0x06D4)---

    CR_BN0_TRX_WDT3_MASK_AGC[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_AGC_CR_BN0_TRX_WDT3_MASK_AGC_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_AGC_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_AGC_CR_BN0_TRX_WDT3_MASK_AGC_MASK 0x000003FF                // CR_BN0_TRX_WDT3_MASK_AGC[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_AGC_CR_BN0_TRX_WDT3_MASK_AGC_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_CTRL_RXFE (0x82000000 + 0x06D8)---

    CR_BN0_TRX_WDT3_COUNT_RXFE[15..0] - (RW) [DE] BBP control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BN0_TRX_WDT3_COND_RXFE[30] - (RW) [DE] BBP control CR
    CR_BN0_TRX_WDT3_ENA_RXFE[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_ENA_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_ENA_RXFE_MASK 0x80000000                // CR_BN0_TRX_WDT3_ENA_RXFE[31]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_ENA_RXFE_SHFT 31
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_COND_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_COND_RXFE_MASK 0x40000000                // CR_BN0_TRX_WDT3_COND_RXFE[30]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_COND_RXFE_SHFT 30
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_COUNT_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_COUNT_RXFE_MASK 0x0000FFFF                // CR_BN0_TRX_WDT3_COUNT_RXFE[15..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_CTRL_RXFE_CR_BN0_TRX_WDT3_COUNT_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_MASK_RXFE (0x82000000 + 0x06DC)---

    CR_BN0_TRX_WDT3_MASK_RXFE[9..0] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXFE_CR_BN0_TRX_WDT3_MASK_RXFE_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXFE_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXFE_CR_BN0_TRX_WDT3_MASK_RXFE_MASK 0x000003FF                // CR_BN0_TRX_WDT3_MASK_RXFE[9..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_MASK_RXFE_CR_BN0_TRX_WDT3_MASK_RXFE_SHFT 0

/* =====================================================================================

  ---CR_BN0_TRX_WDT3_STAT_CTRL (0x82000000 + 0x06E0)---

    CR_BN0_TRX_WDT3_STAT_SELECT[2..0] - (RW) [DE] BBP control CR
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_STAT_CTRL_CR_BN0_TRX_WDT3_STAT_SELECT_ADDR WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_STAT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_STAT_CTRL_CR_BN0_TRX_WDT3_STAT_SELECT_MASK 0x00000007                // CR_BN0_TRX_WDT3_STAT_SELECT[2..0]
#define WF_PHYRX_CTRL_CR_BN0_TRX_WDT3_STAT_CTRL_CR_BN0_TRX_WDT3_STAT_SELECT_SHFT 0

/* =====================================================================================

  ---RO_BN0_TRX_WDT3_STAT_FUNIT (0x82000000 + 0x06E4)---

    RO_BN0_TRX_WDT3_STAT_FUNIT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_FUNIT_RO_BN0_TRX_WDT3_STAT_FUNIT_ADDR WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_FUNIT_ADDR
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_FUNIT_RO_BN0_TRX_WDT3_STAT_FUNIT_MASK 0xFFFFFFFF                // RO_BN0_TRX_WDT3_STAT_FUNIT[31..0]
#define WF_PHYRX_CTRL_RO_BN0_TRX_WDT3_STAT_FUNIT_RO_BN0_TRX_WDT3_STAT_FUNIT_SHFT 0

/* =====================================================================================

  ---CR_DBGCNT1 (0x82000000 + 0x0700)---

    CR_DBGCNT_START_SEL[3..0]    - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_1_SEL[7..4]    - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_2_SEL[11..8]   - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_3_SEL[15..12]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_4_SEL[19..16]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_5_SEL[23..20]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_6_SEL[27..24]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_7_SEL[31..28]  - (RW) DBGCNT: Source Selection

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_7_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_7_SEL_MASK      0xF0000000                // CR_DBGCNT_MID_7_SEL[31..28]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_7_SEL_SHFT      28
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_6_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_6_SEL_MASK      0x0F000000                // CR_DBGCNT_MID_6_SEL[27..24]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_6_SEL_SHFT      24
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_5_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_5_SEL_MASK      0x00F00000                // CR_DBGCNT_MID_5_SEL[23..20]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_5_SEL_SHFT      20
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_4_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_4_SEL_MASK      0x000F0000                // CR_DBGCNT_MID_4_SEL[19..16]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_4_SEL_SHFT      16
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_3_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_3_SEL_MASK      0x0000F000                // CR_DBGCNT_MID_3_SEL[15..12]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_3_SEL_SHFT      12
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_2_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_2_SEL_MASK      0x00000F00                // CR_DBGCNT_MID_2_SEL[11..8]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_2_SEL_SHFT      8
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_1_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_1_SEL_MASK      0x000000F0                // CR_DBGCNT_MID_1_SEL[7..4]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_MID_1_SEL_SHFT      4
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_START_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_START_SEL_MASK      0x0000000F                // CR_DBGCNT_START_SEL[3..0]
#define WF_PHYRX_CTRL_CR_DBGCNT1_CR_DBGCNT_START_SEL_SHFT      0

/* =====================================================================================

  ---CR_DBGCNT2 (0x82000000 + 0x0704)---

    CR_DBGCNT_MID_8_SEL[3..0]    - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_9_SEL[7..4]    - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_A_SEL[11..8]   - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_B_SEL[15..12]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_C_SEL[19..16]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_D_SEL[23..20]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_E_SEL[27..24]  - (RW) DBGCNT: Source Selection
    CR_DBGCNT_MID_F_SEL[31..28]  - (RW) DBGCNT: Source Selection

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_F_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_F_SEL_MASK      0xF0000000                // CR_DBGCNT_MID_F_SEL[31..28]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_F_SEL_SHFT      28
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_E_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_E_SEL_MASK      0x0F000000                // CR_DBGCNT_MID_E_SEL[27..24]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_E_SEL_SHFT      24
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_D_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_D_SEL_MASK      0x00F00000                // CR_DBGCNT_MID_D_SEL[23..20]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_D_SEL_SHFT      20
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_C_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_C_SEL_MASK      0x000F0000                // CR_DBGCNT_MID_C_SEL[19..16]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_C_SEL_SHFT      16
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_B_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_B_SEL_MASK      0x0000F000                // CR_DBGCNT_MID_B_SEL[15..12]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_B_SEL_SHFT      12
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_A_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_A_SEL_MASK      0x00000F00                // CR_DBGCNT_MID_A_SEL[11..8]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_A_SEL_SHFT      8
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_9_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_9_SEL_MASK      0x000000F0                // CR_DBGCNT_MID_9_SEL[7..4]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_9_SEL_SHFT      4
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_8_SEL_ADDR      WF_PHYRX_CTRL_CR_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_8_SEL_MASK      0x0000000F                // CR_DBGCNT_MID_8_SEL[3..0]
#define WF_PHYRX_CTRL_CR_DBGCNT2_CR_DBGCNT_MID_8_SEL_SHFT      0

/* =====================================================================================

  ---CR_DBGCNT3 (0x82000000 + 0x0708)---

    CR_DBGCNT_SHIFT[3..0]        - (RW) DBGCNT: Counter Resolution
                                     4'd0: 6.25ns
                                     4'd1: 12.5ns
                                     4'd2: 25ns
                                     4'd3: 50ns
                                     4'd4: 100ns
                                     4'd15:204.8us
    CR_DBGCNT_RST_MANUAL[4]      - (RW) DBGCNT: Source Selection
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_DBGCNT_RST_ENAB[11..8]    - (RW) DBGCNT: Reset Enable Method
                                     bit[0]: From Mux Select Trig Reset
                                     bit[1]: Manual Reset
                                     bit[2]: Reserved
                                     bit[3]: Reserved
    CR_DBGCNT_RSTLOCK_SEL[15..12] - (RW) DBGCNT: Reset lock source selection
    CR_DBGCNT_RSTLOCK_VALUE[31..16] - (RW) DBGCNT: Reset lock threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RSTLOCK_VALUE_ADDR  WF_PHYRX_CTRL_CR_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RSTLOCK_VALUE_MASK  0xFFFF0000                // CR_DBGCNT_RSTLOCK_VALUE[31..16]
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RSTLOCK_VALUE_SHFT  16
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RSTLOCK_SEL_ADDR    WF_PHYRX_CTRL_CR_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RSTLOCK_SEL_MASK    0x0000F000                // CR_DBGCNT_RSTLOCK_SEL[15..12]
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RSTLOCK_SEL_SHFT    12
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RST_ENAB_ADDR       WF_PHYRX_CTRL_CR_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RST_ENAB_MASK       0x00000F00                // CR_DBGCNT_RST_ENAB[11..8]
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RST_ENAB_SHFT       8
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RST_MANUAL_ADDR     WF_PHYRX_CTRL_CR_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RST_MANUAL_MASK     0x00000010                // CR_DBGCNT_RST_MANUAL[4]
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_RST_MANUAL_SHFT     4
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_SHIFT_ADDR          WF_PHYRX_CTRL_CR_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_SHIFT_MASK          0x0000000F                // CR_DBGCNT_SHIFT[3..0]
#define WF_PHYRX_CTRL_CR_DBGCNT3_CR_DBGCNT_SHIFT_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT1 (0x82000000 + 0x0710)---

    RO_DBGCNT_COUNTER[15..0]     - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_1[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT1_RO_DBGCNT_MID_1_ADDR          WF_PHYRX_CTRL_RO_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT1_RO_DBGCNT_MID_1_MASK          0xFFFF0000                // RO_DBGCNT_MID_1[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT1_RO_DBGCNT_MID_1_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT1_RO_DBGCNT_COUNTER_ADDR        WF_PHYRX_CTRL_RO_DBGCNT1_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT1_RO_DBGCNT_COUNTER_MASK        0x0000FFFF                // RO_DBGCNT_COUNTER[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT1_RO_DBGCNT_COUNTER_SHFT        0

/* =====================================================================================

  ---RO_DBGCNT2 (0x82000000 + 0x0714)---

    RO_DBGCNT_MID_2[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_3[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT2_RO_DBGCNT_MID_3_ADDR          WF_PHYRX_CTRL_RO_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT2_RO_DBGCNT_MID_3_MASK          0xFFFF0000                // RO_DBGCNT_MID_3[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT2_RO_DBGCNT_MID_3_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT2_RO_DBGCNT_MID_2_ADDR          WF_PHYRX_CTRL_RO_DBGCNT2_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT2_RO_DBGCNT_MID_2_MASK          0x0000FFFF                // RO_DBGCNT_MID_2[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT2_RO_DBGCNT_MID_2_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT3 (0x82000000 + 0x0718)---

    RO_DBGCNT_MID_4[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_5[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT3_RO_DBGCNT_MID_5_ADDR          WF_PHYRX_CTRL_RO_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT3_RO_DBGCNT_MID_5_MASK          0xFFFF0000                // RO_DBGCNT_MID_5[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT3_RO_DBGCNT_MID_5_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT3_RO_DBGCNT_MID_4_ADDR          WF_PHYRX_CTRL_RO_DBGCNT3_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT3_RO_DBGCNT_MID_4_MASK          0x0000FFFF                // RO_DBGCNT_MID_4[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT3_RO_DBGCNT_MID_4_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT4 (0x82000000 + 0x071C)---

    RO_DBGCNT_MID_6[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_7[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT4_RO_DBGCNT_MID_7_ADDR          WF_PHYRX_CTRL_RO_DBGCNT4_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT4_RO_DBGCNT_MID_7_MASK          0xFFFF0000                // RO_DBGCNT_MID_7[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT4_RO_DBGCNT_MID_7_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT4_RO_DBGCNT_MID_6_ADDR          WF_PHYRX_CTRL_RO_DBGCNT4_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT4_RO_DBGCNT_MID_6_MASK          0x0000FFFF                // RO_DBGCNT_MID_6[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT4_RO_DBGCNT_MID_6_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT5 (0x82000000 + 0x0720)---

    RO_DBGCNT_MID_8[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_9[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT5_RO_DBGCNT_MID_9_ADDR          WF_PHYRX_CTRL_RO_DBGCNT5_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT5_RO_DBGCNT_MID_9_MASK          0xFFFF0000                // RO_DBGCNT_MID_9[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT5_RO_DBGCNT_MID_9_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT5_RO_DBGCNT_MID_8_ADDR          WF_PHYRX_CTRL_RO_DBGCNT5_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT5_RO_DBGCNT_MID_8_MASK          0x0000FFFF                // RO_DBGCNT_MID_8[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT5_RO_DBGCNT_MID_8_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT6 (0x82000000 + 0x0724)---

    RO_DBGCNT_MID_A[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_B[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT6_RO_DBGCNT_MID_B_ADDR          WF_PHYRX_CTRL_RO_DBGCNT6_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT6_RO_DBGCNT_MID_B_MASK          0xFFFF0000                // RO_DBGCNT_MID_B[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT6_RO_DBGCNT_MID_B_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT6_RO_DBGCNT_MID_A_ADDR          WF_PHYRX_CTRL_RO_DBGCNT6_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT6_RO_DBGCNT_MID_A_MASK          0x0000FFFF                // RO_DBGCNT_MID_A[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT6_RO_DBGCNT_MID_A_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT7 (0x82000000 + 0x0728)---

    RO_DBGCNT_MID_C[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_D[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT7_RO_DBGCNT_MID_D_ADDR          WF_PHYRX_CTRL_RO_DBGCNT7_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT7_RO_DBGCNT_MID_D_MASK          0xFFFF0000                // RO_DBGCNT_MID_D[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT7_RO_DBGCNT_MID_D_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT7_RO_DBGCNT_MID_C_ADDR          WF_PHYRX_CTRL_RO_DBGCNT7_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT7_RO_DBGCNT_MID_C_MASK          0x0000FFFF                // RO_DBGCNT_MID_C[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT7_RO_DBGCNT_MID_C_SHFT          0

/* =====================================================================================

  ---RO_DBGCNT8 (0x82000000 + 0x072C)---

    RO_DBGCNT_MID_E[15..0]       - (RO) DBGCNT: RO_CNT
    RO_DBGCNT_MID_F[31..16]      - (RO) DBGCNT: RO_CNT

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_DBGCNT8_RO_DBGCNT_MID_F_ADDR          WF_PHYRX_CTRL_RO_DBGCNT8_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT8_RO_DBGCNT_MID_F_MASK          0xFFFF0000                // RO_DBGCNT_MID_F[31..16]
#define WF_PHYRX_CTRL_RO_DBGCNT8_RO_DBGCNT_MID_F_SHFT          16
#define WF_PHYRX_CTRL_RO_DBGCNT8_RO_DBGCNT_MID_E_ADDR          WF_PHYRX_CTRL_RO_DBGCNT8_ADDR
#define WF_PHYRX_CTRL_RO_DBGCNT8_RO_DBGCNT_MID_E_MASK          0x0000FFFF                // RO_DBGCNT_MID_E[15..0]
#define WF_PHYRX_CTRL_RO_DBGCNT8_RO_DBGCNT_MID_E_SHFT          0

/* =====================================================================================

  ---CR_RDD_TOP_0 (0x82000000 + 0x0800)---

    CR_HPF_ALPHA_BW20_0[2..0]    - (RW) alpha value for BW20
    CR_HPF_ALPHA_BW20_1[5..3]    - (RW) alpha value for BW20 (state = 1)
    CR_HPF_ALPHA_BW40_0[8..6]    - (RW) alpha value for BW40
    CR_HPF_ALPHA_BW40_1[11..9]   - (RW) alpha value for BW40 (state = 1)
    CR_HPF_STATE_CNT_TH[14..12]  - (RW) HPF state counter threshold for state = 1
    CR_ACI_IGNORE_DC[15]         - (RW) Ignore DC when ACI
    CR_HPF_ALPHA_BW80_0[18..16]  - (RW) alpha value for BW80
    CR_HPF_ALPHA_BW80_1[21..19]  - (RW) alpha value for BW80 (state = 1)
    CR_HPF_ALPHA_BW160_0[24..22] - (RW) alpha value for BW160
    CR_HPF_ALPHA_BW160_1[27..25] - (RW) alpha value for BW160 (state = 1)
    CR_GSWITCH_SETTLE_PRD[30..28] - (RW) agc gain switch settling period
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_GSWITCH_SETTLE_PRD_ADDR  WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_GSWITCH_SETTLE_PRD_MASK  0x70000000                // CR_GSWITCH_SETTLE_PRD[30..28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_GSWITCH_SETTLE_PRD_SHFT  28
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW160_1_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW160_1_MASK   0x0E000000                // CR_HPF_ALPHA_BW160_1[27..25]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW160_1_SHFT   25
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW160_0_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW160_0_MASK   0x01C00000                // CR_HPF_ALPHA_BW160_0[24..22]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW160_0_SHFT   22
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW80_1_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW80_1_MASK    0x00380000                // CR_HPF_ALPHA_BW80_1[21..19]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW80_1_SHFT    19
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW80_0_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW80_0_MASK    0x00070000                // CR_HPF_ALPHA_BW80_0[18..16]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW80_0_SHFT    16
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_ACI_IGNORE_DC_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_ACI_IGNORE_DC_MASK       0x00008000                // CR_ACI_IGNORE_DC[15]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_ACI_IGNORE_DC_SHFT       15
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_STATE_CNT_TH_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_STATE_CNT_TH_MASK    0x00007000                // CR_HPF_STATE_CNT_TH[14..12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_STATE_CNT_TH_SHFT    12
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW40_1_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW40_1_MASK    0x00000E00                // CR_HPF_ALPHA_BW40_1[11..9]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW40_1_SHFT    9
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW40_0_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW40_0_MASK    0x000001C0                // CR_HPF_ALPHA_BW40_0[8..6]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW40_0_SHFT    6
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW20_1_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW20_1_MASK    0x00000038                // CR_HPF_ALPHA_BW20_1[5..3]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW20_1_SHFT    3
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW20_0_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW20_0_MASK    0x00000007                // CR_HPF_ALPHA_BW20_0[2..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_0_CR_HPF_ALPHA_BW20_0_SHFT    0

/* =====================================================================================

  ---CR_RDD_TOP_1 (0x82000000 + 0x0804)---

    CR_DELTA_RSSI_AACI_TH[4..0]  - (RW) delta rssi thrshold for AACI
    RESERVED5[5]                 - (RO) Reserved bits
    CR_MIMOPS_RST_PATH_SEL[6]    - (RW) select MIMOPS rst path of FCBW == 1
    CR_FCBW_RST_PATH_SEL[7]      - (RW) select FCBW rst path of FCBW == 1
                                     1 : means self rst 0: other rst
    CR_DELTA_RSSI_ACI_TH[12..8]  - (RW) delta rssi thrshold for ACI
    RESERVED13[13]               - (RO) Reserved bits
    CR_BAND1_FCBW_ARESET_EN[14]  - (RW) when FCBW happens, do async reset to RDD
    CR_BAND0_FCBW_ARESET_EN[15]  - (RW) when FCBW happens, do async reset to RDD
    CR_MIN_VALID_RSSI_WB_DBV[22..16] - (RW) min RSSI ib value for aci detection
    RESERVED23[23]               - (RO) Reserved bits
    CR_MAX_VALID_RSSI_IB_DBV[30..24] - (RW) max RSSI ib value for aci detection
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MAX_VALID_RSSI_IB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MAX_VALID_RSSI_IB_DBV_MASK 0x7F000000                // CR_MAX_VALID_RSSI_IB_DBV[30..24]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MAX_VALID_RSSI_IB_DBV_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MIN_VALID_RSSI_WB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MIN_VALID_RSSI_WB_DBV_MASK 0x007F0000                // CR_MIN_VALID_RSSI_WB_DBV[22..16]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MIN_VALID_RSSI_WB_DBV_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_BAND0_FCBW_ARESET_EN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_BAND0_FCBW_ARESET_EN_MASK 0x00008000                // CR_BAND0_FCBW_ARESET_EN[15]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_BAND0_FCBW_ARESET_EN_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_BAND1_FCBW_ARESET_EN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_BAND1_FCBW_ARESET_EN_MASK 0x00004000                // CR_BAND1_FCBW_ARESET_EN[14]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_BAND1_FCBW_ARESET_EN_SHFT 14
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_DELTA_RSSI_ACI_TH_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_DELTA_RSSI_ACI_TH_MASK   0x00001F00                // CR_DELTA_RSSI_ACI_TH[12..8]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_DELTA_RSSI_ACI_TH_SHFT   8
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_FCBW_RST_PATH_SEL_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_FCBW_RST_PATH_SEL_MASK   0x00000080                // CR_FCBW_RST_PATH_SEL[7]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_FCBW_RST_PATH_SEL_SHFT   7
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MIMOPS_RST_PATH_SEL_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MIMOPS_RST_PATH_SEL_MASK 0x00000040                // CR_MIMOPS_RST_PATH_SEL[6]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_MIMOPS_RST_PATH_SEL_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_DELTA_RSSI_AACI_TH_ADDR  WF_PHYRX_CTRL_CR_RDD_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_DELTA_RSSI_AACI_TH_MASK  0x0000001F                // CR_DELTA_RSSI_AACI_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_1_CR_DELTA_RSSI_AACI_TH_SHFT  0

/* =====================================================================================

  ---CR_RDD_TOP_2 (0x82000000 + 0x0808)---

    CR_DELTA_RSSI_0_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_DELTA_RSSI_1_TH_ACI[11..6] - (RW) delta rssi threshold when aci_det =1
    CR_AMSC_FAIL_RATIO_ACI[15..12] - (RW) ratio of amplitude stability check when aci_det =1
    CR_DELTA_RSSI_0_TH_SEN[21..16] - (RW) delta rssi threshold when aci_det =0
    CR_DELTA_RSSI_1_TH_SEN[27..22] - (RW) delta rssi threshold when aci_det =0
    CR_AMSC_FAIL_RATIO_SEN[31..28] - (RW) ratio of amplitude stability check when aci_det =0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_AMSC_FAIL_RATIO_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_AMSC_FAIL_RATIO_SEN_MASK 0xF0000000                // CR_AMSC_FAIL_RATIO_SEN[31..28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_AMSC_FAIL_RATIO_SEN_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_1_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_1_TH_SEN_MASK 0x0FC00000                // CR_DELTA_RSSI_1_TH_SEN[27..22]
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_1_TH_SEN_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_0_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_0_TH_SEN_MASK 0x003F0000                // CR_DELTA_RSSI_0_TH_SEN[21..16]
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_0_TH_SEN_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_AMSC_FAIL_RATIO_ACI_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_AMSC_FAIL_RATIO_ACI_MASK 0x0000F000                // CR_AMSC_FAIL_RATIO_ACI[15..12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_AMSC_FAIL_RATIO_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_1_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_1_TH_ACI_MASK 0x00000FC0                // CR_DELTA_RSSI_1_TH_ACI[11..6]
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_1_TH_ACI_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_0_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_0_TH_ACI_MASK 0x0000003F                // CR_DELTA_RSSI_0_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_2_CR_DELTA_RSSI_0_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD_TOP_3 (0x82000000 + 0x080C)---

    CR_DELTA_RSSI_2_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_DELTA_RSSI_2_TH_SEN[11..6] - (RW) delta rssi threshold when aci_det =0
    CR_NO_RISE_EDGE_FIX_GAIN_ENB[12] - (RW) no edge detection when agc fix gain
    CR_FIRST_RISE_EDGE_ENB[13]   - (RW) enable first rise edge as pulse
    RESERVED14[14]               - (RO) Reserved bits
    CR_MAX_PULSE_WIDTH[23..15]   - (RW) maximum pulse width
    CR_MIN_RSSI_DBM[31..24]      - (RW) mininum rssi_dbm value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_MIN_RSSI_DBM_ADDR        WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_MIN_RSSI_DBM_MASK        0xFF000000                // CR_MIN_RSSI_DBM[31..24]
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_MIN_RSSI_DBM_SHFT        24
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_MAX_PULSE_WIDTH_ADDR     WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_MAX_PULSE_WIDTH_MASK     0x00FF8000                // CR_MAX_PULSE_WIDTH[23..15]
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_MAX_PULSE_WIDTH_SHFT     15
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_FIRST_RISE_EDGE_ENB_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_FIRST_RISE_EDGE_ENB_MASK 0x00002000                // CR_FIRST_RISE_EDGE_ENB[13]
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_FIRST_RISE_EDGE_ENB_SHFT 13
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_NO_RISE_EDGE_FIX_GAIN_ENB_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_NO_RISE_EDGE_FIX_GAIN_ENB_MASK 0x00001000                // CR_NO_RISE_EDGE_FIX_GAIN_ENB[12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_NO_RISE_EDGE_FIX_GAIN_ENB_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_DELTA_RSSI_2_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_DELTA_RSSI_2_TH_SEN_MASK 0x00000FC0                // CR_DELTA_RSSI_2_TH_SEN[11..6]
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_DELTA_RSSI_2_TH_SEN_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_DELTA_RSSI_2_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_DELTA_RSSI_2_TH_ACI_MASK 0x0000003F                // CR_DELTA_RSSI_2_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_3_CR_DELTA_RSSI_2_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD_TOP_4 (0x82000000 + 0x0810)---

    CR_SC_DROP_RATIO[3..0]       - (RW) stability drop ration
    CR_SC_CHECK_CNT_DROP[9..4]   - (RW) stability check counter value for drop
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_SC_PASS_RATIO[15..12]     - (RW) stability pass ratio
    CR_SC_CHECK_CNT_PASS[21..16] - (RW) stability check counter value for pass
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_MIN_PULSE_POWER[31..24]   - (RW) mininum pulse power

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_MIN_PULSE_POWER_ADDR     WF_PHYRX_CTRL_CR_RDD_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_MIN_PULSE_POWER_MASK     0xFF000000                // CR_MIN_PULSE_POWER[31..24]
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_MIN_PULSE_POWER_SHFT     24
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_CHECK_CNT_PASS_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_CHECK_CNT_PASS_MASK   0x003F0000                // CR_SC_CHECK_CNT_PASS[21..16]
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_CHECK_CNT_PASS_SHFT   16
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_PASS_RATIO_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_PASS_RATIO_MASK       0x0000F000                // CR_SC_PASS_RATIO[15..12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_PASS_RATIO_SHFT       12
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_CHECK_CNT_DROP_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_CHECK_CNT_DROP_MASK   0x000003F0                // CR_SC_CHECK_CNT_DROP[9..4]
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_CHECK_CNT_DROP_SHFT   4
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_DROP_RATIO_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_DROP_RATIO_MASK       0x0000000F                // CR_SC_DROP_RATIO[3..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_4_CR_SC_DROP_RATIO_SHFT       0

/* =====================================================================================

  ---CR_RDD_TOP_5 (0x82000000 + 0x0814)---

    CR_WAKE_UP_PERIOD[7..0]      - (RW) send wake up IRQ after this value * 0.8192 ms
    CR_WAKE_UP_PULSE_NUM[12..8]  - (RW) send wake up IRQ when pulse number exceed this value
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_NO_DET_PULSE_PERIOD[20..16] - (RW) send SW reset if no det_pulse during this value * 0.84 sec
    RESERVED21[21]               - (RO) Reserved bits
    CR_RDD_ERROR_IRQ_EN[22]      - (RW) Enable interrupt (IRQ) when RDD wake up
    CR_RDD_WAKEUP_IRQ_EN[23]     - (RW) Enable interrupt (IRQ) when RDD error
    CR_PULSE_BUF_SEL[27..24]     - (RW) select read out pulse number
    CR_PULSE_BUF_CLR[28]         - (RW) clear pulse buffer and reset to 0
    RESERVED29[29]               - (RO) Reserved bits
    CR_TEST_DET_PULSE[30]        - (RW) Manually generate pulse rise edge
    CR_TEST_PULSE_EN[31]         - (RW) Send 32'haaaa_bbbb & 32'hcccc_dddd to AHB wrapper

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_TEST_PULSE_EN_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_TEST_PULSE_EN_MASK       0x80000000                // CR_TEST_PULSE_EN[31]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_TEST_PULSE_EN_SHFT       31
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_TEST_DET_PULSE_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_TEST_DET_PULSE_MASK      0x40000000                // CR_TEST_DET_PULSE[30]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_TEST_DET_PULSE_SHFT      30
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_PULSE_BUF_CLR_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_PULSE_BUF_CLR_MASK       0x10000000                // CR_PULSE_BUF_CLR[28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_PULSE_BUF_CLR_SHFT       28
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_PULSE_BUF_SEL_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_PULSE_BUF_SEL_MASK       0x0F000000                // CR_PULSE_BUF_SEL[27..24]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_PULSE_BUF_SEL_SHFT       24
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_RDD_WAKEUP_IRQ_EN_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_RDD_WAKEUP_IRQ_EN_MASK   0x00800000                // CR_RDD_WAKEUP_IRQ_EN[23]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_RDD_WAKEUP_IRQ_EN_SHFT   23
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_RDD_ERROR_IRQ_EN_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_RDD_ERROR_IRQ_EN_MASK    0x00400000                // CR_RDD_ERROR_IRQ_EN[22]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_RDD_ERROR_IRQ_EN_SHFT    22
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_NO_DET_PULSE_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_NO_DET_PULSE_PERIOD_MASK 0x001F0000                // CR_NO_DET_PULSE_PERIOD[20..16]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_NO_DET_PULSE_PERIOD_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_WAKE_UP_PULSE_NUM_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_WAKE_UP_PULSE_NUM_MASK   0x00001F00                // CR_WAKE_UP_PULSE_NUM[12..8]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_WAKE_UP_PULSE_NUM_SHFT   8
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_WAKE_UP_PERIOD_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_WAKE_UP_PERIOD_MASK      0x000000FF                // CR_WAKE_UP_PERIOD[7..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_5_CR_WAKE_UP_PERIOD_SHFT      0

/* =====================================================================================

  ---CR_RDD_TOP_6 (0x82000000 + 0x0818)---

    RO_BAND0_RDD_PULSE_BUF_NUM[4..0] - (RO) Number of pulses stored in buffer
    RESERVED5[7..5]              - (RO) Reserved bits
    RO_BAND0_RDD_WAKEUP_IRQ[8]   - (RO) RDD wake up interrupt
    RO_BAND0_RDD_ERROR_IRQ[9]    - (RO) RDD error interrupt
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_ERROR_IRQ_MASK 0x00000200                // RO_BAND0_RDD_ERROR_IRQ[9]
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_ERROR_IRQ_SHFT 9
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_WAKEUP_IRQ_MASK 0x00000100                // RO_BAND0_RDD_WAKEUP_IRQ[8]
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_WAKEUP_IRQ_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_PULSE_BUF_NUM_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_PULSE_BUF_NUM_MASK 0x0000001F                // RO_BAND0_RDD_PULSE_BUF_NUM[4..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_6_RO_BAND0_RDD_PULSE_BUF_NUM_SHFT 0

/* =====================================================================================

  ---CR_RDD_TOP_7 (0x82000000 + 0x081C)---

    RO_BAND0_RDD_PULSE_BUF_MSB[31..0] - (RO) Read out pulse data for FPGA debug (MSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_7_RO_BAND0_RDD_PULSE_BUF_MSB_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_7_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_7_RO_BAND0_RDD_PULSE_BUF_MSB_MASK 0xFFFFFFFF                // RO_BAND0_RDD_PULSE_BUF_MSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_7_RO_BAND0_RDD_PULSE_BUF_MSB_SHFT 0

/* =====================================================================================

  ---CR_RDD_TOP_8 (0x82000000 + 0x0820)---

    RO_BAND0_RDD_PULSE_BUF_LSB[31..0] - (RO) Read out pulse data for FPGA debug (LSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_8_RO_BAND0_RDD_PULSE_BUF_LSB_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_8_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_8_RO_BAND0_RDD_PULSE_BUF_LSB_MASK 0xFFFFFFFF                // RO_BAND0_RDD_PULSE_BUF_LSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_8_RO_BAND0_RDD_PULSE_BUF_LSB_SHFT 0

/* =====================================================================================

  ---CR_RDD_TOP_12 (0x82000000 + 0x0830)---

    CR_RDD_MDRDY_START[6..0]     - (RW) RDD MDRDY start time
    CR_RDD_MDRDY_END[13..7]      - (RW) RDD MDRDY end time
    CR_RDD_MDRDY_SEL[14]         - (RW) MDRDY select, 0: MDRDY raising, 1: MDRDY trigger
    RESERVED15[24..15]           - (RO) Reserved bits
    CR_RDD0_CCA_SEL[26..25]      - (RW) [DE] BBP control CR
    CR_RDD0_BAND_SEL[27]         - (RW) [DE] BBP control CR
    CR_RDD0_ANT_SEL[29..28]      - (RW) [DE] BBP control CR
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_ANT_SEL_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_ANT_SEL_MASK       0x30000000                // CR_RDD0_ANT_SEL[29..28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_ANT_SEL_SHFT       28
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_BAND_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_BAND_SEL_MASK      0x08000000                // CR_RDD0_BAND_SEL[27]
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_BAND_SEL_SHFT      27
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_CCA_SEL_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_CCA_SEL_MASK       0x06000000                // CR_RDD0_CCA_SEL[26..25]
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD0_CCA_SEL_SHFT       25
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_SEL_MASK      0x00004000                // CR_RDD_MDRDY_SEL[14]
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_SEL_SHFT      14
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_END_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_END_MASK      0x00003F80                // CR_RDD_MDRDY_END[13..7]
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_END_SHFT      7
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_START_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_START_MASK    0x0000007F                // CR_RDD_MDRDY_START[6..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_12_CR_RDD_MDRDY_START_SHFT    0

/* =====================================================================================

  ---CR_RDD_TOP_13 (0x82000000 + 0x0834)---

    CR_DC_RATIO_TH[4..0]         - (RW) dc pulse cnt ratio
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_MIN_RSSI_0_DBV_FOR_ED[14..8] - (RW) DBV for ED
    RESERVED15[20..15]           - (RO) Reserved bits
    CR_ACI_EXIST_RATIO[25..21]   - (RW) cr ACI exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD_DISA_2BST[28]         - (RW) 1: Disable only one 2nd subband exist
                                     it means we can hold 3 subband as high
    CR_RDD_MH_ALGO_NEW[29]       - (RW) MH method use new algo in 7668, 0 use 6632
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_RDD_MH_ALGO_NEW_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_RDD_MH_ALGO_NEW_MASK    0x20000000                // CR_RDD_MH_ALGO_NEW[29]
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_RDD_MH_ALGO_NEW_SHFT    29
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_RDD_DISA_2BST_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_RDD_DISA_2BST_MASK      0x10000000                // CR_RDD_DISA_2BST[28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_RDD_DISA_2BST_SHFT      28
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_ACI_EXIST_RATIO_ADDR    WF_PHYRX_CTRL_CR_RDD_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_ACI_EXIST_RATIO_MASK    0x03E00000                // CR_ACI_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_ACI_EXIST_RATIO_SHFT    21
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_MIN_RSSI_0_DBV_FOR_ED_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_MIN_RSSI_0_DBV_FOR_ED_MASK 0x00007F00                // CR_MIN_RSSI_0_DBV_FOR_ED[14..8]
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_MIN_RSSI_0_DBV_FOR_ED_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_DC_RATIO_TH_ADDR        WF_PHYRX_CTRL_CR_RDD_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_DC_RATIO_TH_MASK        0x0000001F                // CR_DC_RATIO_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_13_CR_DC_RATIO_TH_SHFT        0

/* =====================================================================================

  ---CR_RDD_TOP_14 (0x82000000 + 0x0838)---

    CR_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0] - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12] - (RW) min cnt of ACI
    CR_DC_EXIST_RATIO[25..21]    - (RW) cr dc exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD_RSSI_MAX_2ND_DIFF[31..28] - (RW) subband RSSI comparison,
                                     max subband and 2nd subband threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_RDD_RSSI_MAX_2ND_DIFF_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_RDD_RSSI_MAX_2ND_DIFF_MASK 0xF0000000                // CR_RDD_RSSI_MAX_2ND_DIFF[31..28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_RDD_RSSI_MAX_2ND_DIFF_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_DC_EXIST_RATIO_ADDR     WF_PHYRX_CTRL_CR_RDD_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_DC_EXIST_RATIO_MASK     0x03E00000                // CR_DC_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_DC_EXIST_RATIO_SHFT     21
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_MASK 0x001FF000                // CR_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_MASK 0x000001FF                // CR_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_14_CR_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_SHFT 0

/* =====================================================================================

  ---CR_RDD_TOP_15 (0x82000000 + 0x083C)---

    CR_MIN_LP_WIDTH[8..0]        - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_MAX_PP_WIDTH[20..12]      - (RW) min cnt of ACI
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_ACI_CNT_AACI[27..24]      - (RW) aaci initial value
    CR_ACI_CNT_MAX[31..28]       - (RW) aci maxinum value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_ACI_CNT_MAX_ADDR        WF_PHYRX_CTRL_CR_RDD_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_ACI_CNT_MAX_MASK        0xF0000000                // CR_ACI_CNT_MAX[31..28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_ACI_CNT_MAX_SHFT        28
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_ACI_CNT_AACI_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_ACI_CNT_AACI_MASK       0x0F000000                // CR_ACI_CNT_AACI[27..24]
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_ACI_CNT_AACI_SHFT       24
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_MAX_PP_WIDTH_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_MAX_PP_WIDTH_MASK       0x001FF000                // CR_MAX_PP_WIDTH[20..12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_MAX_PP_WIDTH_SHFT       12
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_MIN_LP_WIDTH_ADDR       WF_PHYRX_CTRL_CR_RDD_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_MIN_LP_WIDTH_MASK       0x000001FF                // CR_MIN_LP_WIDTH[8..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_15_CR_MIN_LP_WIDTH_SHFT       0

/* =====================================================================================

  ---CR_RDD_TOP_16 (0x82000000 + 0x0840)---

    CR_ACI_CHECK_PRD[4..0]       - (RW) accumulation period times of RSSI update
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_CNT_ACI_DET_DROP[12..8]   - (RW) threshold for detction of ACI times per 4us
    RESERVED13[19..13]           - (RO) Reserved bits
    CR_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20] - (RW) count for aci min pulse check
    CR_BAND0_IQC_0_GAINSET[29]   - (RW) when AGC gain settling we force IQC output as 0
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_BAND0_IQC_0_GAINSET_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_BAND0_IQC_0_GAINSET_MASK 0x20000000                // CR_BAND0_IQC_0_GAINSET[29]
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_BAND0_IQC_0_GAINSET_SHFT 29
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_MAX_PULSE_WIDTH_DO_ACI_CHECK_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_MAX_PULSE_WIDTH_DO_ACI_CHECK_MASK 0x1FF00000                // CR_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20]
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_MAX_PULSE_WIDTH_DO_ACI_CHECK_SHFT 20
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_CNT_ACI_DET_DROP_ADDR   WF_PHYRX_CTRL_CR_RDD_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_CNT_ACI_DET_DROP_MASK   0x00001F00                // CR_CNT_ACI_DET_DROP[12..8]
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_CNT_ACI_DET_DROP_SHFT   8
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_ACI_CHECK_PRD_ADDR      WF_PHYRX_CTRL_CR_RDD_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_ACI_CHECK_PRD_MASK      0x0000001F                // CR_ACI_CHECK_PRD[4..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_16_CR_ACI_CHECK_PRD_SHFT      0

/* =====================================================================================

  ---CR_RDD_TOP_17 (0x82000000 + 0x0844)---

    CR_BAND1_DELTA_RSSI_0_TH_SEN[5..0] - (RW) delta rssi threshold when aci_det =0
    CR_BAND1_DELTA_RSSI_1_TH_SEN[11..6] - (RW) delta rssi threshold when aci_det =0
    CR_BAND1_DELTA_RSSI_2_TH_SEN[17..12] - (RW) delta rssi threshold when aci_det =0
    CR_BAND1_IQC_0_GAINSET[18]   - (RW) when AGC gain settling we force IQC output as 0
    CR_BAND1_GSWITCH_SETTLE_PRD[21..19] - (RW) agc gain switch settling period
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_ACI_CNT_L[27..24]         - (RW) aci_cnt threshold
    CR_ACI_CNT_H[31..28]         - (RW) aci_cnt threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_ACI_CNT_H_ADDR          WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_ACI_CNT_H_MASK          0xF0000000                // CR_ACI_CNT_H[31..28]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_ACI_CNT_H_SHFT          28
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_ACI_CNT_L_ADDR          WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_ACI_CNT_L_MASK          0x0F000000                // CR_ACI_CNT_L[27..24]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_ACI_CNT_L_SHFT          24
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_GSWITCH_SETTLE_PRD_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_GSWITCH_SETTLE_PRD_MASK 0x00380000                // CR_BAND1_GSWITCH_SETTLE_PRD[21..19]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_GSWITCH_SETTLE_PRD_SHFT 19
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_IQC_0_GAINSET_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_IQC_0_GAINSET_MASK 0x00040000                // CR_BAND1_IQC_0_GAINSET[18]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_IQC_0_GAINSET_SHFT 18
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_2_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_2_TH_SEN_MASK 0x0003F000                // CR_BAND1_DELTA_RSSI_2_TH_SEN[17..12]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_2_TH_SEN_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_1_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_1_TH_SEN_MASK 0x00000FC0                // CR_BAND1_DELTA_RSSI_1_TH_SEN[11..6]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_1_TH_SEN_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_0_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_0_TH_SEN_MASK 0x0000003F                // CR_BAND1_DELTA_RSSI_0_TH_SEN[5..0]
#define WF_PHYRX_CTRL_CR_RDD_TOP_17_CR_BAND1_DELTA_RSSI_0_TH_SEN_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHY_CTRL_0 (0x82000000 + 0x1000)---

    CR_BAND0_20BW_HT_ACI[0]      - (RW) [DE] BBP control CR
    CR_BAND0_20BW_LG_ACI[1]      - (RW) [DE] BBP control CR
    CR_BAND0_HT_BW_CTRL[3..2]    - (RW) [DE] BBP control CR
    CR_BAND0_LG_BW_CTRL[5..4]    - (RW) [DE] BBP control CR
    CR_BAND0_CCK_ACI_CTRL[6]     - (RW) [DE] BBP control CR
    CR_BAND0_LG_LEN_CTRL[7]      - (RW) [DE] BBP control CR
    CR_BAND0_HT_ACI_CTRL[11..8]  - (RW) [DE] BBP control CR
    CR_BAND0_LG_ACI_CTRL[15..12] - (RW) [DE] BBP control CR
    CR_BAND0_SEC_CH[18..16]      - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND0_PRI_CH[22..20]      - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND0_CBW[27..24]         - (RW) [DE] BBP control CR
    CR_BAND0_BAND[30..28]        - (RW) 0: 2G Band
                                     1: 5G Band
                                     2: Japan Mode 10M BW
                                     3: Japan Mode 5M BW
    CR_BAND0_EN[31]              - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_EN_ADDR     WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_EN_MASK     0x80000000                // CR_BAND0_EN[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_EN_SHFT     31
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_BAND_ADDR   WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_BAND_MASK   0x70000000                // CR_BAND0_BAND[30..28]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_BAND_SHFT   28
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_CBW_ADDR    WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_CBW_MASK    0x0F000000                // CR_BAND0_CBW[27..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_CBW_SHFT    24
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_PRI_CH_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_PRI_CH_MASK 0x00700000                // CR_BAND0_PRI_CH[22..20]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_PRI_CH_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_SEC_CH_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_SEC_CH_MASK 0x00070000                // CR_BAND0_SEC_CH[18..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_SEC_CH_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_ACI_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_ACI_CTRL_MASK 0x0000F000                // CR_BAND0_LG_ACI_CTRL[15..12]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_ACI_CTRL_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_HT_ACI_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_HT_ACI_CTRL_MASK 0x00000F00                // CR_BAND0_HT_ACI_CTRL[11..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_HT_ACI_CTRL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_LEN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_LEN_CTRL_MASK 0x00000080                // CR_BAND0_LG_LEN_CTRL[7]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_LEN_CTRL_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_CCK_ACI_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_CCK_ACI_CTRL_MASK 0x00000040                // CR_BAND0_CCK_ACI_CTRL[6]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_CCK_ACI_CTRL_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_BW_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_BW_CTRL_MASK 0x00000030                // CR_BAND0_LG_BW_CTRL[5..4]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_LG_BW_CTRL_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_HT_BW_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_HT_BW_CTRL_MASK 0x0000000C                // CR_BAND0_HT_BW_CTRL[3..2]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_HT_BW_CTRL_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_20BW_LG_ACI_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_20BW_LG_ACI_MASK 0x00000002                // CR_BAND0_20BW_LG_ACI[1]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_20BW_LG_ACI_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_20BW_HT_ACI_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_20BW_HT_ACI_MASK 0x00000001                // CR_BAND0_20BW_HT_ACI[0]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_0_CR_BAND0_20BW_HT_ACI_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHY_CTRL_1 (0x82000000 + 0x1004)---

    CR_BAND0_HND_VHT_CTRL[7..0]  - (RW) [DE] BBP control CR
    CR_BAND0_HND_LG_CTRL[15..8]  - (RW) [DE] BBP control CR
    CR_BAND0_HND_HT_CTRL[23..16] - (RW) [DE] BBP control CR
    CR_BAND0_HND_CCK_CTRL[27..24] - (RW) [DE] BBP control CR
    CR_BAND0_HND_CTRL[29..28]    - (RW) [DE] BBP control CR
    CR_BAND0_USA_JPN_MODE[30]    - (RW) [DE] BBP control CR
    CR_BAND0_FSM_CTRL[31]        - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_FSM_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_FSM_CTRL_MASK 0x80000000                // CR_BAND0_FSM_CTRL[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_FSM_CTRL_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_USA_JPN_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_USA_JPN_MODE_MASK 0x40000000                // CR_BAND0_USA_JPN_MODE[30]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_USA_JPN_MODE_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_CTRL_MASK 0x30000000                // CR_BAND0_HND_CTRL[29..28]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_CTRL_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_CCK_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_CCK_CTRL_MASK 0x0F000000                // CR_BAND0_HND_CCK_CTRL[27..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_CCK_CTRL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_HT_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_HT_CTRL_MASK 0x00FF0000                // CR_BAND0_HND_HT_CTRL[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_HT_CTRL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_LG_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_LG_CTRL_MASK 0x0000FF00                // CR_BAND0_HND_LG_CTRL[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_LG_CTRL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_VHT_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_VHT_CTRL_MASK 0x000000FF                // CR_BAND0_HND_VHT_CTRL[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_1_CR_BAND0_HND_VHT_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHY_CTRL_2 (0x82000000 + 0x1008)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND0_DIS_OUTER_LOGRST[16] - (RW) [DE] BBP control CR
    CR_BAND0_SEL_OUTER_LOGRST[17] - (RW) [DE] BBP control CR
    CR_BAND0_DIS_OPOST_LOGRST[18] - (RW) [DE] BBP control CR
    CR_BAND0_SEL_OPOST_LOGRST[19] - (RW) [DE] BBP control CR
    CR_BAND0_LTFNUM_CTRL[20]     - (RW) [DE] BBP control CR
    CR_BAND0_RXAIREND_CTRL[21]   - (RW) [DE] BBP control CR
    CR_BAND0_DIS_11N[22]         - (RW) [DE] BBP control CR
    CR_BAND0_MCS_CTRL[23]        - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_MCS_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_MCS_CTRL_MASK 0x00800000                // CR_BAND0_MCS_CTRL[23]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_MCS_CTRL_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_11N_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_11N_MASK 0x00400000                // CR_BAND0_DIS_11N[22]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_11N_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_RXAIREND_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_RXAIREND_CTRL_MASK 0x00200000                // CR_BAND0_RXAIREND_CTRL[21]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_RXAIREND_CTRL_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_LTFNUM_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_LTFNUM_CTRL_MASK 0x00100000                // CR_BAND0_LTFNUM_CTRL[20]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_LTFNUM_CTRL_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_SEL_OPOST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_SEL_OPOST_LOGRST_MASK 0x00080000                // CR_BAND0_SEL_OPOST_LOGRST[19]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_SEL_OPOST_LOGRST_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_OPOST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_OPOST_LOGRST_MASK 0x00040000                // CR_BAND0_DIS_OPOST_LOGRST[18]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_OPOST_LOGRST_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_SEL_OUTER_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_SEL_OUTER_LOGRST_MASK 0x00020000                // CR_BAND0_SEL_OUTER_LOGRST[17]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_SEL_OUTER_LOGRST_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_OUTER_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_OUTER_LOGRST_MASK 0x00010000                // CR_BAND0_DIS_OUTER_LOGRST[16]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_2_CR_BAND0_DIS_OUTER_LOGRST_SHFT 16

/* =====================================================================================

  ---CR_BAND0_PHY_CTRL_3 (0x82000000 + 0x100C)---

    CR_BAND_DLY_FALL_OUTER[7..0] - (RW) [DE] BBP control CR
    CR_BAND_DLY_FALL_OPOST[15..8] - (RW) [DE] BBP control CR
    CR_BAND_DLY_RISE_OUTER[23..16] - (RW) [DE] BBP control CR
    CR_BAND_DLY_RISE_OPOST[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_RISE_OPOST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_RISE_OPOST_MASK 0xFF000000                // CR_BAND_DLY_RISE_OPOST[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_RISE_OPOST_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_RISE_OUTER_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_RISE_OUTER_MASK 0x00FF0000                // CR_BAND_DLY_RISE_OUTER[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_RISE_OUTER_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_FALL_OPOST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_FALL_OPOST_MASK 0x0000FF00                // CR_BAND_DLY_FALL_OPOST[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_FALL_OPOST_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_FALL_OUTER_ADDR WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_FALL_OUTER_MASK 0x000000FF                // CR_BAND_DLY_FALL_OUTER[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHY_CTRL_3_CR_BAND_DLY_FALL_OUTER_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS0 (0x82000000 + 0x1010)---

    RO_BAND0_PHYCTRL_STS0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS0_RO_BAND0_PHYCTRL_STS0_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS0_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS0_RO_BAND0_PHYCTRL_STS0_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS0[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS0_RO_BAND0_PHYCTRL_STS0_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS1 (0x82000000 + 0x1014)---

    RO_BAND0_PHYCTRL_STS1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS1_RO_BAND0_PHYCTRL_STS1_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS1_RO_BAND0_PHYCTRL_STS1_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS1[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS1_RO_BAND0_PHYCTRL_STS1_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS2 (0x82000000 + 0x1018)---

    RO_BAND0_PHYCTRL_STS2[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS2_RO_BAND0_PHYCTRL_STS2_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS2_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS2_RO_BAND0_PHYCTRL_STS2_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS2[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS2_RO_BAND0_PHYCTRL_STS2_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS3 (0x82000000 + 0x101C)---

    RO_BAND0_PHYCTRL_STS3[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS3_RO_BAND0_PHYCTRL_STS3_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS3_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS3_RO_BAND0_PHYCTRL_STS3_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS3[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS3_RO_BAND0_PHYCTRL_STS3_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS4 (0x82000000 + 0x1020)---

    RO_BAND0_PHYCTRL_STS4[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS4_RO_BAND0_PHYCTRL_STS4_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS4_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS4_RO_BAND0_PHYCTRL_STS4_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS4[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS4_RO_BAND0_PHYCTRL_STS4_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS5 (0x82000000 + 0x1024)---

    RO_BAND0_PHYCTRL_STS5[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS5_RO_BAND0_PHYCTRL_STS5_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS5_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS5_RO_BAND0_PHYCTRL_STS5_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS5[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS5_RO_BAND0_PHYCTRL_STS5_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS6 (0x82000000 + 0x1028)---

    RO_BAND0_PHYCTRL_STS6[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS6_RO_BAND0_PHYCTRL_STS6_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS6_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS6_RO_BAND0_PHYCTRL_STS6_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS6[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS6_RO_BAND0_PHYCTRL_STS6_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS7 (0x82000000 + 0x102C)---

    RO_BAND0_PHYCTRL_STS7[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS7_RO_BAND0_PHYCTRL_STS7_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS7_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS7_RO_BAND0_PHYCTRL_STS7_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS7[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS7_RO_BAND0_PHYCTRL_STS7_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS8 (0x82000000 + 0x1030)---

    RO_BAND0_PHYCTRL_STS8[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS8_RO_BAND0_PHYCTRL_STS8_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS8_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS8_RO_BAND0_PHYCTRL_STS8_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS8[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS8_RO_BAND0_PHYCTRL_STS8_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_STS9 (0x82000000 + 0x1034)---

    RO_BAND0_PHYCTRL_STS9[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS9_RO_BAND0_PHYCTRL_STS9_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS9_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS9_RO_BAND0_PHYCTRL_STS9_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS9[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_STS9_RO_BAND0_PHYCTRL_STS9_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_MU (0x82000000 + 0x1038)---

    RO_BAND0_PHYCTRL_STS_MU[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_MU_RO_BAND0_PHYCTRL_STS_MU_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_MU_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_MU_RO_BAND0_PHYCTRL_STS_MU_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS_MU[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_MU_RO_BAND0_PHYCTRL_STS_MU_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYCTRL_FSM (0x82000000 + 0x103C)---

    RO_BAND0_PHYCTRL_STS_FSM[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_FSM_RO_BAND0_PHYCTRL_STS_FSM_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_FSM_RO_BAND0_PHYCTRL_STS_FSM_MASK 0xFFFFFFFF                // RO_BAND0_PHYCTRL_STS_FSM[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYCTRL_FSM_RO_BAND0_PHYCTRL_STS_FSM_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_DBGCTRL (0x82000000 + 0x1040)---

    CR_BAND0_RXFE_ENAB[0]        - (RW) [DE] BBP control CR
    CR_BAND0_RXFE_ENAB_MANU[1]   - (RW) [DE] BBP control CR
    CR_BAND0_RXTD_ENAB[2]        - (RW) [DE] BBP control CR
    CR_BAND0_RXTD_ENAB_MANU[3]   - (RW) [DE] BBP control CR
    CR_BAND0_FFT_ENAB[4]         - (RW) [DE] BBP control CR
    CR_BAND0_FFT_ENAB_MANU[5]    - (RW) [DE] BBP control CR
    CR_BAND0_OPOST_ENAB[6]       - (RW) [DE] BBP control CR
    CR_BAND0_OPOST_ENAB_MANU[7]  - (RW) [DE] BBP control CR
    CR_BAND0_OUTER_ENAB[8]       - (RW) [DE] BBP control CR
    CR_BAND0_OUTER_ENAB_MANU[9]  - (RW) [DE] BBP control CR
    CR_BAND0_CCKRX_ENAB[10]      - (RW) [DE] BBP control CR
    CR_BAND0_CCKRX_ENAB_MANU[11] - (RW) [DE] BBP control CR
    CR_BAND0_MLD_ENAB[12]        - (RW) [DE] BBP control CR
    CR_BAND0_MLD_ENAB_MANU[13]   - (RW) [DE] BBP control CR
    CR_BAND0_LDPC_ENAB[14]       - (RW) [DE] BBP control CR
    CR_BAND0_LDPC_ENAB_MANU[15]  - (RW) [DE] BBP control CR
    CR_BAND0_TXTD_ENAB[16]       - (RW) [DE] BBP control CR
    CR_BAND0_TXTD_ENAB_MANU[17]  - (RW) [DE] BBP control CR
    RESERVED18[19..18]           - (RO) Reserved bits
    CR_BAND0_FFT_TX_ON_MANU[23..20] - (RW) [DE] BBP control CR
    CR_BAND0_POSTST_FSM_CTRL[24] - (RW) [DE] BBP control CR
    RESERVED25[25]               - (RO) Reserved bits
    CR_BAND0_ROLLBACK_FFT_RST[26] - (RW) [DE] BBP control CR
    CR_BAND0_ROLLBACK_AIR_END[27] - (RW) [DE] BBP control CR
    CR_BAND0_TRIG_SEL[31..28]    - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TRIG_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TRIG_SEL_MASK 0xF0000000                // CR_BAND0_TRIG_SEL[31..28]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TRIG_SEL_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_ROLLBACK_AIR_END_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_ROLLBACK_AIR_END_MASK 0x08000000                // CR_BAND0_ROLLBACK_AIR_END[27]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_ROLLBACK_AIR_END_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_ROLLBACK_FFT_RST_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_ROLLBACK_FFT_RST_MASK 0x04000000                // CR_BAND0_ROLLBACK_FFT_RST[26]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_ROLLBACK_FFT_RST_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_POSTST_FSM_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_POSTST_FSM_CTRL_MASK 0x01000000                // CR_BAND0_POSTST_FSM_CTRL[24]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_POSTST_FSM_CTRL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_TX_ON_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_TX_ON_MANU_MASK 0x00F00000                // CR_BAND0_FFT_TX_ON_MANU[23..20]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_TX_ON_MANU_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TXTD_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TXTD_ENAB_MANU_MASK 0x00020000                // CR_BAND0_TXTD_ENAB_MANU[17]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TXTD_ENAB_MANU_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TXTD_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TXTD_ENAB_MASK 0x00010000                // CR_BAND0_TXTD_ENAB[16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_TXTD_ENAB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_LDPC_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_LDPC_ENAB_MANU_MASK 0x00008000                // CR_BAND0_LDPC_ENAB_MANU[15]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_LDPC_ENAB_MANU_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_LDPC_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_LDPC_ENAB_MASK 0x00004000                // CR_BAND0_LDPC_ENAB[14]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_LDPC_ENAB_SHFT 14
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_MLD_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_MLD_ENAB_MANU_MASK 0x00002000                // CR_BAND0_MLD_ENAB_MANU[13]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_MLD_ENAB_MANU_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_MLD_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_MLD_ENAB_MASK 0x00001000                // CR_BAND0_MLD_ENAB[12]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_MLD_ENAB_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_CCKRX_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_CCKRX_ENAB_MANU_MASK 0x00000800                // CR_BAND0_CCKRX_ENAB_MANU[11]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_CCKRX_ENAB_MANU_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_CCKRX_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_CCKRX_ENAB_MASK 0x00000400                // CR_BAND0_CCKRX_ENAB[10]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_CCKRX_ENAB_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OUTER_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OUTER_ENAB_MANU_MASK 0x00000200                // CR_BAND0_OUTER_ENAB_MANU[9]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OUTER_ENAB_MANU_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OUTER_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OUTER_ENAB_MASK 0x00000100                // CR_BAND0_OUTER_ENAB[8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OUTER_ENAB_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OPOST_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OPOST_ENAB_MANU_MASK 0x00000080                // CR_BAND0_OPOST_ENAB_MANU[7]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OPOST_ENAB_MANU_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OPOST_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OPOST_ENAB_MASK 0x00000040                // CR_BAND0_OPOST_ENAB[6]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_OPOST_ENAB_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_ENAB_MANU_MASK 0x00000020                // CR_BAND0_FFT_ENAB_MANU[5]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_ENAB_MANU_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_ENAB_MASK 0x00000010                // CR_BAND0_FFT_ENAB[4]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_FFT_ENAB_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXTD_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXTD_ENAB_MANU_MASK 0x00000008                // CR_BAND0_RXTD_ENAB_MANU[3]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXTD_ENAB_MANU_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXTD_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXTD_ENAB_MASK 0x00000004                // CR_BAND0_RXTD_ENAB[2]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXTD_ENAB_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXFE_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXFE_ENAB_MANU_MASK 0x00000002                // CR_BAND0_RXFE_ENAB_MANU[1]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXFE_ENAB_MANU_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXFE_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXFE_ENAB_MASK 0x00000001                // CR_BAND0_RXFE_ENAB[0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_DBGCTRL_CR_BAND0_RXFE_ENAB_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_POPCTRL (0x82000000 + 0x1044)---

    CR_BAND0_POP_RX_LEN[23..0]   - (RW) [DE] BBP control CR
    RESERVED24[30..24]           - (RO) Reserved bits
    CR_BAND0_POP_FILTER[31]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_CR_BAND0_POP_FILTER_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_CR_BAND0_POP_FILTER_MASK 0x80000000                // CR_BAND0_POP_FILTER[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_CR_BAND0_POP_FILTER_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_CR_BAND0_POP_RX_LEN_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_CR_BAND0_POP_RX_LEN_MASK 0x00FFFFFF                // CR_BAND0_POP_RX_LEN[23..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_POPCTRL_CR_BAND0_POP_RX_LEN_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_RXTD_ENAB (0x82000000 + 0x1048)---

    CR_BAND0_DLY_FALL_RXTD[7..0] - (RW) [DE] BBP control CR
    CR_BAND0_DLY_RISE_RXTD[15..8] - (RW) [DE] BBP control CR
    CR_BAND0_DLY_FALL_RXFE[23..16] - (RW) [DE] BBP control CR
    CR_BAND0_DLY_RISE_RXFE[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_RISE_RXFE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_RISE_RXFE_MASK 0xFF000000                // CR_BAND0_DLY_RISE_RXFE[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_RISE_RXFE_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_FALL_RXFE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_FALL_RXFE_MASK 0x00FF0000                // CR_BAND0_DLY_FALL_RXFE[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_FALL_RXFE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_RISE_RXTD_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_RISE_RXTD_MASK 0x0000FF00                // CR_BAND0_DLY_RISE_RXTD[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_RISE_RXTD_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_FALL_RXTD_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_FALL_RXTD_MASK 0x000000FF                // CR_BAND0_DLY_FALL_RXTD[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RXTD_ENAB_CR_BAND0_DLY_FALL_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_RATE_CTRL (0x82000000 + 0x104C)---

    CR_BAND0_VHT_SPRT_NSS_CHK[7..0] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_SPRT_NDP_CHK[15..8] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_NDP_BYP_SIGB[16] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_NDP_BYP_SNGU[17] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_NDP_BYP_ZLEN[18] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_SYM_CNT_MODE[19] - (RW) [DE] BBP control CR
    CR_BAND0_HT_SPRT_NSS_CHK[23..20] - (RW) [DE] BBP control CR
    CR_BAND0_HT_SPRT_NDP_CHK[27..24] - (RW) [DE] BBP control CR
    CR_BAND0_HT_NDP_BYP_HSIG[28] - (RW) [DE] BBP control CR
    CR_BAND0_HT_NDP_BYP_ZLEN[29] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_SKIP_ANT_CHK[30] - (RW) [DE] BBP control CR
    CR_BAND0_HT_SKIP_ANT_CHK[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SKIP_ANT_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SKIP_ANT_CHK_MASK 0x80000000                // CR_BAND0_HT_SKIP_ANT_CHK[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SKIP_ANT_CHK_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SKIP_ANT_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SKIP_ANT_CHK_MASK 0x40000000                // CR_BAND0_VHT_SKIP_ANT_CHK[30]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SKIP_ANT_CHK_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_NDP_BYP_ZLEN_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_NDP_BYP_ZLEN_MASK 0x20000000                // CR_BAND0_HT_NDP_BYP_ZLEN[29]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_NDP_BYP_ZLEN_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_NDP_BYP_HSIG_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_NDP_BYP_HSIG_MASK 0x10000000                // CR_BAND0_HT_NDP_BYP_HSIG[28]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_NDP_BYP_HSIG_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SPRT_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SPRT_NDP_CHK_MASK 0x0F000000                // CR_BAND0_HT_SPRT_NDP_CHK[27..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SPRT_NDP_CHK_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SPRT_NSS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SPRT_NSS_CHK_MASK 0x00F00000                // CR_BAND0_HT_SPRT_NSS_CHK[23..20]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_HT_SPRT_NSS_CHK_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SYM_CNT_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SYM_CNT_MODE_MASK 0x00080000                // CR_BAND0_VHT_SYM_CNT_MODE[19]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SYM_CNT_MODE_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_ZLEN_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_ZLEN_MASK 0x00040000                // CR_BAND0_VHT_NDP_BYP_ZLEN[18]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_ZLEN_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_SNGU_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_SNGU_MASK 0x00020000                // CR_BAND0_VHT_NDP_BYP_SNGU[17]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_SNGU_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_SIGB_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_SIGB_MASK 0x00010000                // CR_BAND0_VHT_NDP_BYP_SIGB[16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_NDP_BYP_SIGB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SPRT_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SPRT_NDP_CHK_MASK 0x0000FF00                // CR_BAND0_VHT_SPRT_NDP_CHK[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SPRT_NDP_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SPRT_NSS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SPRT_NSS_CHK_MASK 0x000000FF                // CR_BAND0_VHT_SPRT_NSS_CHK[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_RATE_CTRL_CR_BAND0_VHT_SPRT_NSS_CHK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_GIDTAB (0x82000000 + 0x1050)---

    B0_CM_GID_TAB_UPD_ALL[0]     - (RW) [DE] BBP control CR
    B0_CM_GID_TAB_CLR_ALL[1]     - (RW) [DE] BBP control CR
    RESERVED2[15..2]             - (RO) Reserved bits
    CR_BAND0_GID_TAB_TEST_GID[21..16] - (RW) [DE] BBP control CR
    RESERVED22[23..22]           - (RO) Reserved bits
    B0_CM_GID_TAB_TEST_UPD[24]   - (RW) [DE] BBP control CR
    RESERVED25[30..25]           - (RO) Reserved bits
    CR_BAND0_GID_TAB_TEST_MODE[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_CR_BAND0_GID_TAB_TEST_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_CR_BAND0_GID_TAB_TEST_MODE_MASK 0x80000000                // CR_BAND0_GID_TAB_TEST_MODE[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_CR_BAND0_GID_TAB_TEST_MODE_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_TEST_UPD_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_TEST_UPD_MASK 0x01000000                // B0_CM_GID_TAB_TEST_UPD[24]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_TEST_UPD_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_CR_BAND0_GID_TAB_TEST_GID_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_CR_BAND0_GID_TAB_TEST_GID_MASK 0x003F0000                // CR_BAND0_GID_TAB_TEST_GID[21..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_CR_BAND0_GID_TAB_TEST_GID_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_CLR_ALL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_CLR_ALL_MASK 0x00000002                // B0_CM_GID_TAB_CLR_ALL[1]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_CLR_ALL_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_UPD_ALL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_UPD_ALL_MASK 0x00000001                // B0_CM_GID_TAB_UPD_ALL[0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_GIDTAB_B0_CM_GID_TAB_UPD_ALL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_GID_TAB_VLD_0 (0x82000000 + 0x1054)---

    RESERVED0[0]                 - (RO) Reserved bits
    CR_BAND0_GID_TAB_VLD_0[31..1] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_0_CR_BAND0_GID_TAB_VLD_0_ADDR WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_0_CR_BAND0_GID_TAB_VLD_0_MASK 0xFFFFFFFE                // CR_BAND0_GID_TAB_VLD_0[31..1]
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_0_CR_BAND0_GID_TAB_VLD_0_SHFT 1

/* =====================================================================================

  ---CR_BAND0_GID_TAB_VLD_1 (0x82000000 + 0x1058)---

    CR_BAND0_GID_TAB_VLD_1[30..0] - (RW) [DE] BBP control CR
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_1_CR_BAND0_GID_TAB_VLD_1_ADDR WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_1_CR_BAND0_GID_TAB_VLD_1_MASK 0x7FFFFFFF                // CR_BAND0_GID_TAB_VLD_1[30..0]
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_VLD_1_CR_BAND0_GID_TAB_VLD_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_GID_TAB_POS_0 (0x82000000 + 0x105C)---

    RESERVED0[1..0]              - (RO) Reserved bits
    CR_BAND0_GID_TAB_POS_0[31..2] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_0_CR_BAND0_GID_TAB_POS_0_ADDR WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_0_CR_BAND0_GID_TAB_POS_0_MASK 0xFFFFFFFC                // CR_BAND0_GID_TAB_POS_0[31..2]
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_0_CR_BAND0_GID_TAB_POS_0_SHFT 2

/* =====================================================================================

  ---CR_BAND0_GID_TAB_POS_1 (0x82000000 + 0x1060)---

    CR_BAND0_GID_TAB_POS_1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_1_CR_BAND0_GID_TAB_POS_1_ADDR WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_1_CR_BAND0_GID_TAB_POS_1_MASK 0xFFFFFFFF                // CR_BAND0_GID_TAB_POS_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_1_CR_BAND0_GID_TAB_POS_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_GID_TAB_POS_2 (0x82000000 + 0x1064)---

    CR_BAND0_GID_TAB_POS_2[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_2_CR_BAND0_GID_TAB_POS_2_ADDR WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_2_CR_BAND0_GID_TAB_POS_2_MASK 0xFFFFFFFF                // CR_BAND0_GID_TAB_POS_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_2_CR_BAND0_GID_TAB_POS_2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_GID_TAB_POS_3 (0x82000000 + 0x1068)---

    CR_BAND0_GID_TAB_POS_3[29..0] - (RW) [DE] BBP control CR
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_3_CR_BAND0_GID_TAB_POS_3_ADDR WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_3_CR_BAND0_GID_TAB_POS_3_MASK 0x3FFFFFFF                // CR_BAND0_GID_TAB_POS_3[29..0]
#define WF_PHYRX_CTRL_CR_BAND0_GID_TAB_POS_3_CR_BAND0_GID_TAB_POS_3_SHFT 0

/* =====================================================================================

  ---RO_BAND0_GIDTAB_STATUS (0x82000000 + 0x106C)---

    RO_BAND0_GID_TAB_STATUS[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_GIDTAB_STATUS_RO_BAND0_GID_TAB_STATUS_ADDR WF_PHYRX_CTRL_RO_BAND0_GIDTAB_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_GIDTAB_STATUS_RO_BAND0_GID_TAB_STATUS_MASK 0xFFFFFFFF                // RO_BAND0_GID_TAB_STATUS[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_GIDTAB_STATUS_RO_BAND0_GID_TAB_STATUS_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_BF_CTRL (0x82000000 + 0x1080)---

    CR_BAND0_IBF_DIS_LNA_ULG[0]  - (RW) [DE] BBP control CR
    CR_BAND0_IBF_DIS_LNA_LG[1]   - (RW) [DE] BBP control CR
    CR_BAND0_IBF_DIS_LNA_MG[2]   - (RW) [DE] BBP control CR
    CR_BAND0_IBF_DIS_LNA_HG[3]   - (RW) [DE] BBP control CR
    CR_BAND0_IBF_DIS_LNA_DIFF[4] - (RW) [DE] BBP control CR
    CR_BAND0_IBF_SM_BIT_BYPASS[5] - (RW) [DE] BBP control CR
    CR_BAND0_IBF_BF_BIT_BYPASS[6] - (RW) [DE] BBP control CR
    CR_BAND0_IBF_DONE_POLLING_DIS[7] - (RW) [DE] BBP control CR
    CR_BAND0_BFEE_SOUND_N_BYPASS[8] - (RW) [DE] BBP control CR
    CR_BAND0_IBF_DIS_LNA_UHG[9]  - (RW) [DE] BBP control CR
    CR_BAND0_IBF_AGC_QUAL_RX_ON_REV[10] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND0_HT_NDP_BYP_BFEE_SOUND[12] - (RW) [DE] BBP control CR
    RESERVED13[29..13]           - (RO) Reserved bits
    CR_BAND0_ROLLBACK_FFT_NBID[30] - (RW) [DE] BBP control CR
    CR_BAND0_ROLLBACK_FFT_STOP[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_ROLLBACK_FFT_STOP_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_ROLLBACK_FFT_STOP_MASK 0x80000000                // CR_BAND0_ROLLBACK_FFT_STOP[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_ROLLBACK_FFT_STOP_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_ROLLBACK_FFT_NBID_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_ROLLBACK_FFT_NBID_MASK 0x40000000                // CR_BAND0_ROLLBACK_FFT_NBID[30]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_ROLLBACK_FFT_NBID_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_HT_NDP_BYP_BFEE_SOUND_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_HT_NDP_BYP_BFEE_SOUND_MASK 0x00001000                // CR_BAND0_HT_NDP_BYP_BFEE_SOUND[12]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_HT_NDP_BYP_BFEE_SOUND_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_AGC_QUAL_RX_ON_REV_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_AGC_QUAL_RX_ON_REV_MASK 0x00000400                // CR_BAND0_IBF_AGC_QUAL_RX_ON_REV[10]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_AGC_QUAL_RX_ON_REV_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_UHG_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_UHG_MASK 0x00000200                // CR_BAND0_IBF_DIS_LNA_UHG[9]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_UHG_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_BFEE_SOUND_N_BYPASS_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_BFEE_SOUND_N_BYPASS_MASK 0x00000100                // CR_BAND0_BFEE_SOUND_N_BYPASS[8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_BFEE_SOUND_N_BYPASS_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DONE_POLLING_DIS_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DONE_POLLING_DIS_MASK 0x00000080                // CR_BAND0_IBF_DONE_POLLING_DIS[7]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DONE_POLLING_DIS_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_BF_BIT_BYPASS_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_BF_BIT_BYPASS_MASK 0x00000040                // CR_BAND0_IBF_BF_BIT_BYPASS[6]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_BF_BIT_BYPASS_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_SM_BIT_BYPASS_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_SM_BIT_BYPASS_MASK 0x00000020                // CR_BAND0_IBF_SM_BIT_BYPASS[5]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_SM_BIT_BYPASS_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_DIFF_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_DIFF_MASK 0x00000010                // CR_BAND0_IBF_DIS_LNA_DIFF[4]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_DIFF_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_HG_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_HG_MASK 0x00000008                // CR_BAND0_IBF_DIS_LNA_HG[3]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_HG_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_MG_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_MG_MASK 0x00000004                // CR_BAND0_IBF_DIS_LNA_MG[2]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_MG_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_LG_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_LG_MASK 0x00000002                // CR_BAND0_IBF_DIS_LNA_LG[1]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_LG_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_ULG_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_ULG_MASK 0x00000001                // CR_BAND0_IBF_DIS_LNA_ULG[0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_BF_CTRL_CR_BAND0_IBF_DIS_LNA_ULG_SHFT 0

/* =====================================================================================

  ---CR_BAND0_SIG_DEC_CTRL (0x82000000 + 0x1090)---

    CR_BAND0_LGSIG_LEN_CHK[0]    - (RW) 1: Enable, 0: disable
    CR_BAND0_LGSIG_NDP_CHK[1]    - (RW) 1: Enable, 0: disable
    CR_BAND0_LGSIG_R4_CHK[2]     - (RW) [DE] BBP control CR
    CR_BAND0_LGSIG_PARITY_CHK[3] - (RW) [DE] BBP control CR
    CR_BAND0_HTSIG_LEN_CHK[4]    - (RW) 1: Enable, 0: disable
    CR_BAND0_HTSIG_NDP_CHK[5]    - (RW) 1: Enable, 0: disable
    CR_BAND0_HTSIG_CBW_CHK[6]    - (RW) 1: Enable, 0: disable
    CR_BAND0_HTSIG_RATE_CHK[7]   - (RW) 1: Enable, 0: disable
    CR_BAND0_VHTSIGA_LEN_CHK[8]  - (RW) 1: Enable, 0: disable
    CR_BAND0_VHTSIGA_NDP_CHK[9]  - (RW) 1: Enable, 0: disable
    CR_BAND0_VHTSIGA_CBW_CHK[10] - (RW) 1: Enable, 0: disable
    CR_BAND0_VHTSIGA_DBW_CHK[11] - (RW) 1: Enable, 0: disable
    CR_BAND0_VHTSIGA_RATE_CHK[12] - (RW) 1: Enable, 0: disable
    CR_BAND0_VHTSIGB_CHK[15..13] - (RW) Bit[15] 1: enable RX_VLD_ALL_STS check; 0: Bypass
                                     Bit[14] 1: enable SIGB check in MU; 0: Disable
                                     Bit[13] 1: enable SIGB check in SU; 0: Disable
    CR_BAND0_RXVEC_BW_RPT_TYPE[17..16] - (RW) 00: RX_BW, which is updated by BWD & SIGNAL Field
                                     01: POST BWD Results
                                     10: RXTD CBW2DBW Ratio
                                     11: Force CBW to BW20
    CR_BAND0_DIS_RXTD_FFT_RST[18] - (RW) 1: Disable FFT Reset from RXTD
                                     0: Enable
    CR_BAND0_HT_SKIP_STBC_CHK[19] - (RW) 1: Enable, 0: Disable
    CR_BAND0_HTSIG_STBC_CHK[20]  - (RW) 1: Enable, 0: Disable
    CR_BAND0_HT_NDP_BYP_STBC[21] - (RW) 1: Enable, 0: Disable
    CR_BAND0_HT_SKIP_MCS_CHK[22] - (RW) 1: Enable, 1: Disable
    CR_BAND0_HTSIG_NLTF_CHK[23]  - (RW) [DE] BBP control CR
    CR_BAND0_VHT_SKIP_STBC_CHK[24] - (RW) 1: Enable, 0: Disable
    CR_BAND0_VHT_SKIP_MCS_CHK[25] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_DIS_MU_PPDU[26] - (RW) 1: Disable MU_PPDU RX
                                     0: Allow MU PPDU RX
    CR_BAND0_VHT_ALL_STS_CHK[27] - (RW) [DE] BBP control CR
    CR_BAND0_VHT_IEEE_MCS_ONLY[28] - (RW) [DE] BBP control CR
    CR_BAND0_CCK_SKIP_SHORT_ERR[29] - (RW) [DE] BBP control CR
    CR_BAND0_DISABLE_NESS_UNSPRT[30] - (RW) Reserved CR
    CR_BAND0_DISABLE_LDPC_UNSPRT[31] - (RW) Reserved CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DISABLE_LDPC_UNSPRT_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DISABLE_LDPC_UNSPRT_MASK 0x80000000                // CR_BAND0_DISABLE_LDPC_UNSPRT[31]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DISABLE_LDPC_UNSPRT_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DISABLE_NESS_UNSPRT_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DISABLE_NESS_UNSPRT_MASK 0x40000000                // CR_BAND0_DISABLE_NESS_UNSPRT[30]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DISABLE_NESS_UNSPRT_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_CCK_SKIP_SHORT_ERR_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_CCK_SKIP_SHORT_ERR_MASK 0x20000000                // CR_BAND0_CCK_SKIP_SHORT_ERR[29]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_CCK_SKIP_SHORT_ERR_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_IEEE_MCS_ONLY_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_IEEE_MCS_ONLY_MASK 0x10000000                // CR_BAND0_VHT_IEEE_MCS_ONLY[28]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_IEEE_MCS_ONLY_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_ALL_STS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_ALL_STS_CHK_MASK 0x08000000                // CR_BAND0_VHT_ALL_STS_CHK[27]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_ALL_STS_CHK_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_DIS_MU_PPDU_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_DIS_MU_PPDU_MASK 0x04000000                // CR_BAND0_VHT_DIS_MU_PPDU[26]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_DIS_MU_PPDU_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_SKIP_MCS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_SKIP_MCS_CHK_MASK 0x02000000                // CR_BAND0_VHT_SKIP_MCS_CHK[25]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_SKIP_MCS_CHK_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_SKIP_STBC_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_SKIP_STBC_CHK_MASK 0x01000000                // CR_BAND0_VHT_SKIP_STBC_CHK[24]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHT_SKIP_STBC_CHK_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_NLTF_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_NLTF_CHK_MASK 0x00800000                // CR_BAND0_HTSIG_NLTF_CHK[23]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_NLTF_CHK_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_SKIP_MCS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_SKIP_MCS_CHK_MASK 0x00400000                // CR_BAND0_HT_SKIP_MCS_CHK[22]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_SKIP_MCS_CHK_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_NDP_BYP_STBC_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_NDP_BYP_STBC_MASK 0x00200000                // CR_BAND0_HT_NDP_BYP_STBC[21]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_NDP_BYP_STBC_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_STBC_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_STBC_CHK_MASK 0x00100000                // CR_BAND0_HTSIG_STBC_CHK[20]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_STBC_CHK_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_SKIP_STBC_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_SKIP_STBC_CHK_MASK 0x00080000                // CR_BAND0_HT_SKIP_STBC_CHK[19]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HT_SKIP_STBC_CHK_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DIS_RXTD_FFT_RST_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DIS_RXTD_FFT_RST_MASK 0x00040000                // CR_BAND0_DIS_RXTD_FFT_RST[18]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_DIS_RXTD_FFT_RST_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_RXVEC_BW_RPT_TYPE_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_RXVEC_BW_RPT_TYPE_MASK 0x00030000                // CR_BAND0_RXVEC_BW_RPT_TYPE[17..16]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_RXVEC_BW_RPT_TYPE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGB_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGB_CHK_MASK 0x0000E000                // CR_BAND0_VHTSIGB_CHK[15..13]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGB_CHK_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_RATE_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_RATE_CHK_MASK 0x00001000                // CR_BAND0_VHTSIGA_RATE_CHK[12]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_RATE_CHK_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_DBW_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_DBW_CHK_MASK 0x00000800                // CR_BAND0_VHTSIGA_DBW_CHK[11]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_DBW_CHK_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_CBW_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_CBW_CHK_MASK 0x00000400                // CR_BAND0_VHTSIGA_CBW_CHK[10]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_CBW_CHK_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_NDP_CHK_MASK 0x00000200                // CR_BAND0_VHTSIGA_NDP_CHK[9]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_NDP_CHK_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_LEN_CHK_MASK 0x00000100                // CR_BAND0_VHTSIGA_LEN_CHK[8]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_VHTSIGA_LEN_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_RATE_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_RATE_CHK_MASK 0x00000080                // CR_BAND0_HTSIG_RATE_CHK[7]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_RATE_CHK_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_CBW_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_CBW_CHK_MASK 0x00000040                // CR_BAND0_HTSIG_CBW_CHK[6]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_CBW_CHK_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_NDP_CHK_MASK 0x00000020                // CR_BAND0_HTSIG_NDP_CHK[5]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_NDP_CHK_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_LEN_CHK_MASK 0x00000010                // CR_BAND0_HTSIG_LEN_CHK[4]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_HTSIG_LEN_CHK_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_PARITY_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_PARITY_CHK_MASK 0x00000008                // CR_BAND0_LGSIG_PARITY_CHK[3]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_PARITY_CHK_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_R4_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_R4_CHK_MASK 0x00000004                // CR_BAND0_LGSIG_R4_CHK[2]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_R4_CHK_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_NDP_CHK_MASK 0x00000002                // CR_BAND0_LGSIG_NDP_CHK[1]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_NDP_CHK_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_LEN_CHK_MASK 0x00000001                // CR_BAND0_LGSIG_LEN_CHK[0]
#define WF_PHYRX_CTRL_CR_BAND0_SIG_DEC_CTRL_CR_BAND0_LGSIG_LEN_CHK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_FSM (0x82000000 + 0x1094)---

    CR_BAND0_POSTST_TIMEOUT[7..0] - (RW) [DE] BBP control CR
    CR_BAND0_PREST_TIMEOUT[15..8] - (RW) [DE] BBP control CR
    CR_BAND0_BEAMFORM_TIMEOUT[31..16] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_BEAMFORM_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_BEAMFORM_TIMEOUT_MASK 0xFFFF0000                // CR_BAND0_BEAMFORM_TIMEOUT[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_BEAMFORM_TIMEOUT_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_PREST_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_PREST_TIMEOUT_MASK 0x0000FF00                // CR_BAND0_PREST_TIMEOUT[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_PREST_TIMEOUT_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_POSTST_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_POSTST_TIMEOUT_MASK 0x000000FF                // CR_BAND0_POSTST_TIMEOUT[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_FSM_CR_BAND0_POSTST_TIMEOUT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_AIRST (0x82000000 + 0x1098)---

    CR_BAND0_AIRST_CCKRX_TIMEOUT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[19..16]           - (RO) Reserved bits
    CR_BAND0_CCKRX_TIMER_ADVANCE[27..20] - (RW) [DE] BBP control CR
    CR_BAND0_CCKRX_TIMER_MODE[28] - (RW) [DE] BBP control CR
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_CCKRX_TIMER_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_CCKRX_TIMER_MODE_MASK 0x10000000                // CR_BAND0_CCKRX_TIMER_MODE[28]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_CCKRX_TIMER_MODE_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_CCKRX_TIMER_ADVANCE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_CCKRX_TIMER_ADVANCE_MASK 0x0FF00000                // CR_BAND0_CCKRX_TIMER_ADVANCE[27..20]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_CCKRX_TIMER_ADVANCE_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_AIRST_CCKRX_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_AIRST_CCKRX_TIMEOUT_MASK 0x0000FFFF                // CR_BAND0_AIRST_CCKRX_TIMEOUT[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_AIRST_CR_BAND0_AIRST_CCKRX_TIMEOUT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_ERR (0x82000000 + 0x109C)---

    CR_BAND0_ABERR_MASK[15..0]   - (RW) [DE] BBP control CR
    CR_BAND0_POSTST_WEND_TIMEOUT[23..16] - (RW) [DE] BBP control CR
    CR_BAND0_BBRX_AIREND_TIMEOUT[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_BBRX_AIREND_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_BBRX_AIREND_TIMEOUT_MASK 0xFF000000                // CR_BAND0_BBRX_AIREND_TIMEOUT[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_BBRX_AIREND_TIMEOUT_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_POSTST_WEND_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_POSTST_WEND_TIMEOUT_MASK 0x00FF0000                // CR_BAND0_POSTST_WEND_TIMEOUT[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_POSTST_WEND_TIMEOUT_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_ABERR_MASK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_ABERR_MASK_MASK 0x0000FFFF                // CR_BAND0_ABERR_MASK[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_ERR_CR_BAND0_ABERR_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYCTRL_STSCNTR (0x82000000 + 0x10A0)---

    CR_BAND0_STSCNTR_SEL_RX_0[4..0] - (RW)  xxx
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_BAND0_STSCNTR_SEL_RX_1[12..8] - (RW)  xxx
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_BAND0_STSCNTR_SEL_MU_0[17..16] - (RW)  xxx
    RESERVED18[23..18]           - (RO) Reserved bits
    CR_BAND0_STSCNTR_SEL_MU_1[25..24] - (RW) [DE] BBP Counters
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_MU_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_MU_1_MASK 0x03000000                // CR_BAND0_STSCNTR_SEL_MU_1[25..24]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_MU_1_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_MU_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_MU_0_MASK 0x00030000                // CR_BAND0_STSCNTR_SEL_MU_0[17..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_MU_0_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_RX_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_RX_1_MASK 0x00001F00                // CR_BAND0_STSCNTR_SEL_RX_1[12..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_RX_1_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_RX_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_RX_0_MASK 0x0000001F                // CR_BAND0_STSCNTR_SEL_RX_0[4..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYCTRL_STSCNTR_CR_BAND0_STSCNTR_SEL_RX_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_AIR_TIMER1 (0x82000000 + 0x10B0)---

    CR_BAND0_AIR_TIMER_BW20_ADVANCE[7..0] - (RW) AIR Timer Counter BW20 Adance value, unit: 50ns
    CR_BAND0_AIR_TIMER_BW40_ADVANCE[15..8] - (RW) AIR Timer Counter BW40 Adance value, unit: 50ns
    CR_BAND0_AIR_TIMER_BW80_ADVANCE[23..16] - (RW) AIR Timer Counter BW80 Adance value, unit: 50ns
    CR_BAND0_AIR_TIMER_B160_ADVANCE[31..24] - (RW) AIR Timer Counter BW160 Adance value, unit: 50ns

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_B160_ADVANCE_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_B160_ADVANCE_MASK 0xFF000000                // CR_BAND0_AIR_TIMER_B160_ADVANCE[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_B160_ADVANCE_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW80_ADVANCE_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW80_ADVANCE_MASK 0x00FF0000                // CR_BAND0_AIR_TIMER_BW80_ADVANCE[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW80_ADVANCE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW40_ADVANCE_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW40_ADVANCE_MASK 0x0000FF00                // CR_BAND0_AIR_TIMER_BW40_ADVANCE[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW40_ADVANCE_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW20_ADVANCE_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW20_ADVANCE_MASK 0x000000FF                // CR_BAND0_AIR_TIMER_BW20_ADVANCE[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER1_CR_BAND0_AIR_TIMER_BW20_ADVANCE_SHFT 0

/* =====================================================================================

  ---CR_BAND0_AIR_TIMER2 (0x82000000 + 0x10B4)---

    CR_AE_RSSI_BW20_ADV[7..0]    - (RW) AIR Timer RSSI BW20 Adance value, unit: 50ns
    CR_AE_RSSI_BW40_ADV[15..8]   - (RW) AIR Timer RSSI BW40 Adance value, unit: 50ns
    CR_AE_RSSI_BW80_ADV[23..16]  - (RW) AIR Timer RSSI BW80 Adance value, unit: 50ns
    CR_AE_RSSI_B160_ADV[31..24]  - (RW) AIR Timer RSSI BW160 Adance value, unit: 50ns

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_B160_ADV_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_B160_ADV_MASK 0xFF000000                // CR_AE_RSSI_B160_ADV[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_B160_ADV_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW80_ADV_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW80_ADV_MASK 0x00FF0000                // CR_AE_RSSI_BW80_ADV[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW80_ADV_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW40_ADV_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW40_ADV_MASK 0x0000FF00                // CR_AE_RSSI_BW40_ADV[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW40_ADV_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW20_ADV_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW20_ADV_MASK 0x000000FF                // CR_AE_RSSI_BW20_ADV[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER2_CR_AE_RSSI_BW20_ADV_SHFT 0

/* =====================================================================================

  ---CR_BAND0_AIR_TIMER3 (0x82000000 + 0x10B8)---

    CR_BAND0_DBG_RSSI_TADJ[0]    - (RW) AIR Timer Counter DBG
    CR_BAND0_HE_RXTIME_SEL[1]    - (RW) AIR Timer HE Timer AXE Method
    CR_BAND0_AE_RSSI_DETECT_ENAB[2] - (RW) AIREnd RSSI Detect Enable
    CR_AE_RSSI_COMP_SHGI[3]      - (RW) AIREnd RSSI Detect Enable
    CR_RSSI_AIREND_TH[8..4]      - (RW) AIREnd RXTD RSSI T_ADJ Threshold
    CR_AE_RSSI_TADJ_LIMIT[14..9] - (RW) AIREnd RSSI T_ADJ Limiter for final weighted result (default = 500ns), unit 50ns
    RESERVED15[15]               - (RO) Reserved bits
    CR_AE_DETECT_EXTEND_TIME[22..16] - (RW) AIREnd Timer Detect Window after Air End. (default = 3us), unit: 50ns
    RESERVED23[23]               - (RO) Reserved bits
    CR_AE_DETECT_TARGET_TIME[30..24] - (RW) AIREnd Timer Detect Window before PKT End. (default = 9us), unit: 50ns
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_DETECT_TARGET_TIME_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_DETECT_TARGET_TIME_MASK 0x7F000000                // CR_AE_DETECT_TARGET_TIME[30..24]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_DETECT_TARGET_TIME_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_DETECT_EXTEND_TIME_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_DETECT_EXTEND_TIME_MASK 0x007F0000                // CR_AE_DETECT_EXTEND_TIME[22..16]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_DETECT_EXTEND_TIME_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_RSSI_TADJ_LIMIT_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_RSSI_TADJ_LIMIT_MASK 0x00007E00                // CR_AE_RSSI_TADJ_LIMIT[14..9]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_RSSI_TADJ_LIMIT_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_RSSI_AIREND_TH_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_RSSI_AIREND_TH_MASK 0x000001F0                // CR_RSSI_AIREND_TH[8..4]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_RSSI_AIREND_TH_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_RSSI_COMP_SHGI_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_RSSI_COMP_SHGI_MASK 0x00000008                // CR_AE_RSSI_COMP_SHGI[3]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_AE_RSSI_COMP_SHGI_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_AE_RSSI_DETECT_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_AE_RSSI_DETECT_ENAB_MASK 0x00000004                // CR_BAND0_AE_RSSI_DETECT_ENAB[2]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_AE_RSSI_DETECT_ENAB_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_HE_RXTIME_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_HE_RXTIME_SEL_MASK 0x00000002                // CR_BAND0_HE_RXTIME_SEL[1]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_HE_RXTIME_SEL_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_DBG_RSSI_TADJ_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_DBG_RSSI_TADJ_MASK 0x00000001                // CR_BAND0_DBG_RSSI_TADJ[0]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER3_CR_BAND0_DBG_RSSI_TADJ_SHFT 0

/* =====================================================================================

  ---CR_BAND0_AIR_TIMER4 (0x82000000 + 0x10BC)---

    CR_AE_RSSI_TADJ_W0[2..0]     - (RW) AIREnd Timer RSSI Tadj Weight
    RESERVED3[3]                 - (RO) Reserved bits
    CR_AE_RSSI_TADJ_W1[6..4]     - (RW) AIREnd Timer RSSI Tadj Weight
    RESERVED7[7]                 - (RO) Reserved bits
    CR_AE_RSSI_TADJ_W2[10..8]    - (RW) AIREnd Timer RSSI Tadj Weight
    RESERVED11[11]               - (RO) Reserved bits
    CR_AE_RSSI_TADJ_W3[14..12]   - (RW) AIREnd Timer RSSI Tadj Weight
    RESERVED15[15]               - (RO) Reserved bits
    CR_AE_RSSI_TADJ_W4[18..16]   - (RW) AIREnd Timer RSSI Tadj Weight
    RESERVED19[19]               - (RO) Reserved bits
    CR_AE_RSSI_TADJ_W5[22..20]   - (RW) AIREnd Timer RSSI Tadj Weight
    RESERVED23[31..23]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W5_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W5_MASK 0x00700000                // CR_AE_RSSI_TADJ_W5[22..20]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W5_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W4_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W4_MASK 0x00070000                // CR_AE_RSSI_TADJ_W4[18..16]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W4_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W3_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W3_MASK 0x00007000                // CR_AE_RSSI_TADJ_W3[14..12]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W3_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W2_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W2_MASK 0x00000700                // CR_AE_RSSI_TADJ_W2[10..8]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W2_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W1_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W1_MASK 0x00000070                // CR_AE_RSSI_TADJ_W1[6..4]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W1_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W0_ADDR WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W0_MASK 0x00000007                // CR_AE_RSSI_TADJ_W0[2..0]
#define WF_PHYRX_CTRL_CR_BAND0_AIR_TIMER4_CR_AE_RSSI_TADJ_W0_SHFT 0

/* =====================================================================================

  ---RO_BAND0_AIR_TIMER5 (0x82000000 + 0x10C0)---

    RO_BAND0_DBG_SYM_TARGET_TIME[31..0] - (RO) AirEnd Target Time

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER5_RO_BAND0_DBG_SYM_TARGET_TIME_ADDR WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER5_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER5_RO_BAND0_DBG_SYM_TARGET_TIME_MASK 0xFFFFFFFF                // RO_BAND0_DBG_SYM_TARGET_TIME[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER5_RO_BAND0_DBG_SYM_TARGET_TIME_SHFT 0

/* =====================================================================================

  ---RO_BAND0_AIR_TIMER6 (0x82000000 + 0x10C4)---

    RO_BAND0_DBG_RSSI_TADJ[30..0] - (RO) AirEnd DBG Signals
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER6_RO_BAND0_DBG_RSSI_TADJ_ADDR WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER6_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER6_RO_BAND0_DBG_RSSI_TADJ_MASK 0x7FFFFFFF                // RO_BAND0_DBG_RSSI_TADJ[30..0]
#define WF_PHYRX_CTRL_RO_BAND0_AIR_TIMER6_RO_BAND0_DBG_RSSI_TADJ_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PFD_RXERR_HANDLE (0x82000000 + 0x10D0)---

    CR_BAND0_PFD_RXERR_HANDLE[11..0] - (RW) PFD Handle: 1: RXERR, 0: Normal
    RESERVED12[15..12]           - (RO) Reserved bits
    CR_BAND0_HTSIG_ERRCHK_LGSIG[16] - (RW) RXHT_ERR Handle: 1: Consider LGSIG_ERR, 0: Consider only HT_SIG_ERR
    CR_BAND0_VHTSIGA_ERRCHK_LGSIG[17] - (RW) RXVHT_ERR Handle: 1: Consider LGSIG_ERR, 0: Consider only VHT_SIGA_ERR
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_VHTSIGA_ERRCHK_LGSIG_ADDR WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_VHTSIGA_ERRCHK_LGSIG_MASK 0x00020000                // CR_BAND0_VHTSIGA_ERRCHK_LGSIG[17]
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_VHTSIGA_ERRCHK_LGSIG_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_HTSIG_ERRCHK_LGSIG_ADDR WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_HTSIG_ERRCHK_LGSIG_MASK 0x00010000                // CR_BAND0_HTSIG_ERRCHK_LGSIG[16]
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_HTSIG_ERRCHK_LGSIG_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_PFD_RXERR_HANDLE_ADDR WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_PFD_RXERR_HANDLE_MASK 0x00000FFF                // CR_BAND0_PFD_RXERR_HANDLE[11..0]
#define WF_PHYRX_CTRL_CR_BAND0_PFD_RXERR_HANDLE_CR_BAND0_PFD_RXERR_HANDLE_SHFT 0

/* =====================================================================================

  ---CR_BAND0_RLSIG_CHK (0x82000000 + 0x1100)---

    CR_BAND0_RLSIG_LEN_CHK[0]    - (RW) 1: Enable, 0: disable
    CR_BAND0_RLSIG_M_CHK[1]      - (RW) 1: Enable, 0: disable
    CR_BAND0_RLSIG_R4_CHK[2]     - (RW) 1: Enable, 0: disable
    CR_BAND0_RLSIG_PARITY_CHK[3] - (RW) 1: Enable, 0: disable
    CR_BAND0_RLSIG_RATE_CHK[4]   - (RW) 1: Enable, 0: disable
    CR_BAND0_RLSIG_UPDATE_PARAM[5] - (RW) 1: Enable, 0: disable
    RESERVED6[7..6]              - (RO) Reserved bits
    CR_BAND0_RLSIG_LENGTH_THRESHOLD[19..8] - (RW) Length threshold
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_LENGTH_THRESHOLD_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_LENGTH_THRESHOLD_MASK 0x000FFF00                // CR_BAND0_RLSIG_LENGTH_THRESHOLD[19..8]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_LENGTH_THRESHOLD_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_UPDATE_PARAM_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_UPDATE_PARAM_MASK 0x00000020                // CR_BAND0_RLSIG_UPDATE_PARAM[5]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_UPDATE_PARAM_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_RATE_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_RATE_CHK_MASK 0x00000010                // CR_BAND0_RLSIG_RATE_CHK[4]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_RATE_CHK_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_PARITY_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_PARITY_CHK_MASK 0x00000008                // CR_BAND0_RLSIG_PARITY_CHK[3]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_PARITY_CHK_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_R4_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_R4_CHK_MASK 0x00000004                // CR_BAND0_RLSIG_R4_CHK[2]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_R4_CHK_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_M_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_M_CHK_MASK 0x00000002                // CR_BAND0_RLSIG_M_CHK[1]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_M_CHK_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_LEN_CHK_MASK 0x00000001                // CR_BAND0_RLSIG_LEN_CHK[0]
#define WF_PHYRX_CTRL_CR_BAND0_RLSIG_CHK_CR_BAND0_RLSIG_LEN_CHK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_SU_CHK (0x82000000 + 0x1104)---

    CR_BAND0_HE_SU_BSS_COLOR[5..0] - (RW) HE-SIGA SU for BSS_Color checker:
    CR_BAND0_HE_SU_UL_DL[6]      - (RW) HE-SIGA SU for UL/DL checker:
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND0_HE_SU_SPRT_NSS_CHK[15..8] - (RW) HE-SIGA SU NSS checker:
    CR_BAND0_HESIGA_SU_SKIP_CHK[31..16] - (RW) Skip HE-SIGA SU checker: 1: Skip, 0: Enable_CHK

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HESIGA_SU_SKIP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HESIGA_SU_SKIP_CHK_MASK 0xFFFF0000                // CR_BAND0_HESIGA_SU_SKIP_CHK[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HESIGA_SU_SKIP_CHK_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_SPRT_NSS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_SPRT_NSS_CHK_MASK 0x0000FF00                // CR_BAND0_HE_SU_SPRT_NSS_CHK[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_SPRT_NSS_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_UL_DL_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_UL_DL_MASK 0x00000040                // CR_BAND0_HE_SU_UL_DL[6]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_UL_DL_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_BSS_COLOR_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_BSS_COLOR_MASK 0x0000003F                // CR_BAND0_HE_SU_BSS_COLOR[5..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_SU_CHK_CR_BAND0_HE_SU_BSS_COLOR_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_ER_CHK (0x82000000 + 0x1108)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND0_HESIGA_ER_SKIP_CHK[31..16] - (RW) Skip HE-SIGA ER checker: 1: Skip, 0: Enable_CHK

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ER_CHK_CR_BAND0_HESIGA_ER_SKIP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_ER_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ER_CHK_CR_BAND0_HESIGA_ER_SKIP_CHK_MASK 0xFFFF0000                // CR_BAND0_HESIGA_ER_SKIP_CHK[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ER_CHK_CR_BAND0_HESIGA_ER_SKIP_CHK_SHFT 16

/* =====================================================================================

  ---CR_BAND0_HESIG_TB_CHK (0x82000000 + 0x110C)---

    CR_BAND0_HE_TB_BSS_COLOR[5..0] - (RW) HE-SIGA TB for BSS_Color checker:
    RESERVED6[15..6]             - (RO) Reserved bits
    CR_BAND0_HESIGA_TB_SKIP_CHK[31..16] - (RW) Skip HE-SIGA TB checker: 1: Skip, 0: Enable_CHK

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_CR_BAND0_HESIGA_TB_SKIP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_CR_BAND0_HESIGA_TB_SKIP_CHK_MASK 0xFFFF0000                // CR_BAND0_HESIGA_TB_SKIP_CHK[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_CR_BAND0_HESIGA_TB_SKIP_CHK_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_CR_BAND0_HE_TB_BSS_COLOR_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_CR_BAND0_HE_TB_BSS_COLOR_MASK 0x0000003F                // CR_BAND0_HE_TB_BSS_COLOR[5..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_TB_CHK_CR_BAND0_HE_TB_BSS_COLOR_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_NDP_CHK (0x82000000 + 0x1110)---

    CR_BAND0_HE_NDP_BYP[7..0]    - (RW) HE-SIGA NDP checker: 1: Skip, 0: Enable_CHK
    CR_BAND0_HE_SPRT_NDP_CHK[15..8] - (RW) HE-SIGA NDP NSS checker:
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_CR_BAND0_HE_SPRT_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_CR_BAND0_HE_SPRT_NDP_CHK_MASK 0x0000FF00                // CR_BAND0_HE_SPRT_NDP_CHK[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_CR_BAND0_HE_SPRT_NDP_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_CR_BAND0_HE_NDP_BYP_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_CR_BAND0_HE_NDP_BYP_MASK 0x000000FF                // CR_BAND0_HE_NDP_BYP[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_NDP_CHK_CR_BAND0_HE_NDP_BYP_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_MU_CHK1 (0x82000000 + 0x1114)---

    CR_BAND0_HESIGB_MU_SKIP_CHK[15..0] - (RW) Skip HE-SIGB MU checker: 1: Skip, 0: Enable_CHK
    CR_BAND0_HESIGA_MU_SKIP_CHK[31..16] - (RW) Skip HE-SIGA MU checker: 1: Skip, 0: Enable_CHK

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_CR_BAND0_HESIGA_MU_SKIP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_CR_BAND0_HESIGA_MU_SKIP_CHK_MASK 0xFFFF0000                // CR_BAND0_HESIGA_MU_SKIP_CHK[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_CR_BAND0_HESIGA_MU_SKIP_CHK_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_CR_BAND0_HESIGB_MU_SKIP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_CR_BAND0_HESIGB_MU_SKIP_CHK_MASK 0x0000FFFF                // CR_BAND0_HESIGB_MU_SKIP_CHK[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK1_CR_BAND0_HESIGB_MU_SKIP_CHK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_MU_CHK2 (0x82000000 + 0x1118)---

    CR_BAND0_HE_MU_STBC4MUMIMO[0] - (RW) HE-SIGB MU for STBC for MU-MIMO checker:
    RESERVED1[7..1]              - (RO) Reserved bits
    CR_BAND0_HE_MU_SPRT_NSS_CHK[15..8] - (RW) HE-SIGB MU NSS checker:
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_CR_BAND0_HE_MU_SPRT_NSS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_CR_BAND0_HE_MU_SPRT_NSS_CHK_MASK 0x0000FF00                // CR_BAND0_HE_MU_SPRT_NSS_CHK[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_CR_BAND0_HE_MU_SPRT_NSS_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_CR_BAND0_HE_MU_STBC4MUMIMO_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_CR_BAND0_HE_MU_STBC4MUMIMO_MASK 0x00000001                // CR_BAND0_HE_MU_STBC4MUMIMO[0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_MU_CHK2_CR_BAND0_HE_MU_STBC4MUMIMO_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_ERR_HANDLE1 (0x82000000 + 0x111C)---

    CR_BAND0_HE_MU_ERR_HANDLE[15..0] - (RW) HE-SIGA MU Unsprt/Error Handle: [0]UnsportRate [1]RxErr
    CR_BAND0_HE_SU_ERR_HANDLE[31..16] - (RW) HE-SIGA SU Unsprt/Error Handle: [0]UnsportRate [1]RxErr

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_CR_BAND0_HE_SU_ERR_HANDLE_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_CR_BAND0_HE_SU_ERR_HANDLE_MASK 0xFFFF0000                // CR_BAND0_HE_SU_ERR_HANDLE[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_CR_BAND0_HE_SU_ERR_HANDLE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_CR_BAND0_HE_MU_ERR_HANDLE_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_CR_BAND0_HE_MU_ERR_HANDLE_MASK 0x0000FFFF                // CR_BAND0_HE_MU_ERR_HANDLE[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE1_CR_BAND0_HE_MU_ERR_HANDLE_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_ERR_HANDLE2 (0x82000000 + 0x1120)---

    CR_BAND0_HE_TB_ERR_HANDLE[15..0] - (RW) HE-SIGA TB Unsprt/Error Handle: [0]UnsportRate [1]RxErr
    CR_BAND0_HE_ER_ERR_HANDLE[31..16] - (RW) HE-SIGA ER Unsprt/Error Handle: [0]UnsportRate [1]RxErr

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_CR_BAND0_HE_ER_ERR_HANDLE_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_CR_BAND0_HE_ER_ERR_HANDLE_MASK 0xFFFF0000                // CR_BAND0_HE_ER_ERR_HANDLE[31..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_CR_BAND0_HE_ER_ERR_HANDLE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_CR_BAND0_HE_TB_ERR_HANDLE_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_CR_BAND0_HE_TB_ERR_HANDLE_MASK 0x0000FFFF                // CR_BAND0_HE_TB_ERR_HANDLE[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE2_CR_BAND0_HE_TB_ERR_HANDLE_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_ERR_HANDLE3 (0x82000000 + 0x1124)---

    CR_HESIG_ERR_RST[0]          - (RW) HE-SIG Decoder RESET WHEN Any Error Found
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE3_CR_HESIG_ERR_RST_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE3_CR_HESIG_ERR_RST_MASK 0x00000001                // CR_HESIG_ERR_RST[0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_ERR_HANDLE3_CR_HESIG_ERR_RST_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIG_SU_CHK (0x82000000 + 0x1128)---

    RO_BAND0_HESIGA_SU_CHK[15..0] - (RO) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_SU_CHK_RO_BAND0_HESIGA_SU_CHK_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIG_SU_CHK_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_SU_CHK_RO_BAND0_HESIGA_SU_CHK_MASK 0x0000FFFF                // RO_BAND0_HESIGA_SU_CHK[15..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_SU_CHK_RO_BAND0_HESIGA_SU_CHK_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIG_ER_CHK (0x82000000 + 0x112C)---

    RO_BAND0_HESIGA_ER_CHK[15..0] - (RO) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_ER_CHK_RO_BAND0_HESIGA_ER_CHK_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIG_ER_CHK_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_ER_CHK_RO_BAND0_HESIGA_ER_CHK_MASK 0x0000FFFF                // RO_BAND0_HESIGA_ER_CHK[15..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_ER_CHK_RO_BAND0_HESIGA_ER_CHK_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIG_MU_CHK (0x82000000 + 0x1130)---

    RO_BAND0_HESIGA_MU_CHK[15..0] - (RO) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_MU_CHK_RO_BAND0_HESIGA_MU_CHK_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIG_MU_CHK_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_MU_CHK_RO_BAND0_HESIGA_MU_CHK_MASK 0x0000FFFF                // RO_BAND0_HESIGA_MU_CHK[15..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_MU_CHK_RO_BAND0_HESIGA_MU_CHK_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIG_TB_CHK (0x82000000 + 0x1134)---

    RO_BAND0_HESIGA_TB_CHK[15..0] - (RO) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_TB_CHK_RO_BAND0_HESIGA_TB_CHK_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIG_TB_CHK_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_TB_CHK_RO_BAND0_HESIGA_TB_CHK_MASK 0x0000FFFF                // RO_BAND0_HESIGA_TB_CHK[15..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_TB_CHK_RO_BAND0_HESIGA_TB_CHK_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIG_NDP_CHK (0x82000000 + 0x1138)---

    RO_BAND0_HESIGA_NDP_CHK[7..0] - (RO) [DE] BBP control CR
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_NDP_CHK_RO_BAND0_HESIGA_NDP_CHK_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIG_NDP_CHK_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_NDP_CHK_RO_BAND0_HESIGA_NDP_CHK_MASK 0x000000FF                // RO_BAND0_HESIGA_NDP_CHK[7..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_NDP_CHK_RO_BAND0_HESIGA_NDP_CHK_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIG_PFD (0x82000000 + 0x113C)---

    RO_BAND0_SIGDEC_PFD_CASE[3..0] - (RO) [DE] BBP control CR
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_PFD_RO_BAND0_SIGDEC_PFD_CASE_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIG_PFD_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_PFD_RO_BAND0_SIGDEC_PFD_CASE_MASK 0x0000000F                // RO_BAND0_SIGDEC_PFD_CASE[3..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIG_PFD_RO_BAND0_SIGDEC_PFD_CASE_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_GI (0x82000000 + 0x1140)---

    CR_BAND0_HESU_GI_FOR_00[1..0] - (RW) HE-SIGA SU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HESU_GI_FOR_01[3..2] - (RW) HE-SIGA SU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HESU_GI_FOR_10[5..4] - (RW) HE-SIGA SU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HESU_GI_FOR_11_dcm1_stbc1[7..6] - (RW) HE-SIGA SU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HESU_GI_FOR_11_otherwise[9..8] - (RW) HE-SIGA SU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    RESERVED10[15..10]           - (RO) Reserved bits
    CR_BAND0_HEMU_GI_FOR_00[17..16] - (RW) HE-SIGA MU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HEMU_GI_FOR_01[19..18] - (RW) HE-SIGA MU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HEMU_GI_FOR_10[21..20] - (RW) HE-SIGA MU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    CR_BAND0_HEMU_GI_FOR_11[23..22] - (RW) HE-SIGA MU GI CONFIG: 2'd0:0.8us, 2'd1:1.6us, 2'd2:3.2us
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_11_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_11_MASK 0x00C00000                // CR_BAND0_HEMU_GI_FOR_11[23..22]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_11_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_10_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_10_MASK 0x00300000                // CR_BAND0_HEMU_GI_FOR_10[21..20]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_10_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_01_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_01_MASK 0x000C0000                // CR_BAND0_HEMU_GI_FOR_01[19..18]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_01_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_00_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_00_MASK 0x00030000                // CR_BAND0_HEMU_GI_FOR_00[17..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HEMU_GI_FOR_00_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_11_otherwise_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_11_otherwise_MASK 0x00000300                // CR_BAND0_HESU_GI_FOR_11_otherwise[9..8]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_11_otherwise_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_11_dcm1_stbc1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_11_dcm1_stbc1_MASK 0x000000C0                // CR_BAND0_HESU_GI_FOR_11_dcm1_stbc1[7..6]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_11_dcm1_stbc1_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_10_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_10_MASK 0x00000030                // CR_BAND0_HESU_GI_FOR_10[5..4]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_10_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_01_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_01_MASK 0x0000000C                // CR_BAND0_HESU_GI_FOR_01[3..2]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_01_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_00_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_00_MASK 0x00000003                // CR_BAND0_HESU_GI_FOR_00[1..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_GI_CR_BAND0_HESU_GI_FOR_00_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_LTF (0x82000000 + 0x1144)---

    CR_BAND0_HESU_LTF_FOR_00[1..0] - (RW) HE-SIGA SU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HESU_LTF_FOR_01[3..2] - (RW) HE-SIGA SU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HESU_LTF_FOR_10[5..4] - (RW) HE-SIGA SU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HESU_LTF_FOR_11_dcm1_stbc1[7..6] - (RW) HE-SIGA SU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HESU_LTF_FOR_11_otherwise[9..8] - (RW) HE-SIGA SU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    RESERVED10[15..10]           - (RO) Reserved bits
    CR_BAND0_HEMU_LTF_FOR_00[17..16] - (RW) HE-SIGA MU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HEMU_LTF_FOR_01[19..18] - (RW) HE-SIGA MU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HEMU_LTF_FOR_10[21..20] - (RW) HE-SIGA MU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    CR_BAND0_HEMU_LTF_FOR_11[23..22] - (RW) HE-SIGA MU LTF Size: 2'd0:1x, 2'd1:2x, 2'd2:4x
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_11_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_11_MASK 0x00C00000                // CR_BAND0_HEMU_LTF_FOR_11[23..22]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_11_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_10_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_10_MASK 0x00300000                // CR_BAND0_HEMU_LTF_FOR_10[21..20]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_10_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_01_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_01_MASK 0x000C0000                // CR_BAND0_HEMU_LTF_FOR_01[19..18]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_01_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_00_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_00_MASK 0x00030000                // CR_BAND0_HEMU_LTF_FOR_00[17..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HEMU_LTF_FOR_00_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_11_otherwise_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_11_otherwise_MASK 0x00000300                // CR_BAND0_HESU_LTF_FOR_11_otherwise[9..8]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_11_otherwise_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_11_dcm1_stbc1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_11_dcm1_stbc1_MASK 0x000000C0                // CR_BAND0_HESU_LTF_FOR_11_dcm1_stbc1[7..6]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_11_dcm1_stbc1_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_10_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_10_MASK 0x00000030                // CR_BAND0_HESU_LTF_FOR_10[5..4]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_10_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_01_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_01_MASK 0x0000000C                // CR_BAND0_HESU_LTF_FOR_01[3..2]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_01_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_00_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_00_MASK 0x00000003                // CR_BAND0_HESU_LTF_FOR_00[1..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_LTF_CR_BAND0_HESU_LTF_FOR_00_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIG_A_FACTOR (0x82000000 + 0x1148)---

    CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM0[2..0] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM0[6..4] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM0[10..8] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM0[14..12] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED15[15]               - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM1[18..16] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM1[22..20] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM1[26..24] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM1[30..28] - (RW) HE-SIGA Pre-FEC Padding Factor
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM1_MASK 0x70000000                // CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM1[30..28]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM1_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM1_MASK 0x07000000                // CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM1[26..24]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM1_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM1_MASK 0x00700000                // CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM1[22..20]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM1_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM1_MASK 0x00070000                // CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM1[18..16]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM1_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM0_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM0_MASK 0x00007000                // CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM0[14..12]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_11_LDPC_X_SYM0_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM0_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM0_MASK 0x00000700                // CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM0[10..8]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_10_LDPC_X_SYM0_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM0_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM0_MASK 0x00000070                // CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM0[6..4]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_01_LDPC_X_SYM0_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM0_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM0_MASK 0x00000007                // CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM0[2..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIG_A_FACTOR_CR_BAND0_A_FACTOR_FOR_00_LDPC_X_SYM0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HE_PE_DMBT (0x82000000 + 0x114C)---

    CR_BAND0_PE_DMBT_FOR_0[0]    - (RW) HE-SIGA Disambiguity for 0
    CR_BAND0_PE_DMBT_FOR_1[1]    - (RW) HE-SIGA Disambiguity for 1
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_CR_BAND0_PE_DMBT_FOR_1_ADDR WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_CR_BAND0_PE_DMBT_FOR_1_MASK 0x00000002                // CR_BAND0_PE_DMBT_FOR_1[1]
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_CR_BAND0_PE_DMBT_FOR_1_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_CR_BAND0_PE_DMBT_FOR_0_ADDR WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_CR_BAND0_PE_DMBT_FOR_0_MASK 0x00000001                // CR_BAND0_PE_DMBT_FOR_0[0]
#define WF_PHYRX_CTRL_CR_BAND0_HE_PE_DMBT_CR_BAND0_PE_DMBT_FOR_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HEMU_RULE1 (0x82000000 + 0x1150)---

    CR_BAND0_HEMU_RULE1_AID[10..0] - (RW) HEMU RULE AID:  AID field are used to address the STAs in this field.
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND0_HEMU_RULE1_BSS[21..16] - (RW) HEMU RULE BSS_COLOR: The BSS Color field is an identifier of the BSS
    CR_BAND0_HEMU_RULE1_UDL[22]  - (RW) HEMU RULE UL/DL: Set to 0 for DL, Set to 1 for UL
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE1_AID_EN[24] - (RW) HEMU RULE AID Enable: 0 Disable, 1:Enable
    CR_BAND0_HEMU_RULE1_BSS_EN[25] - (RW) HEMU RULE BSS_COLOR Enable: 0: Disable, 1: Enable
    CR_BAND0_HEMU_RULE1_UDL_EN[26] - (RW) HEMU RULE UL/DL Enable: 0 Disable, 1:Enable
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE1_PRIORITY[30..28] - (RW) HEMU RULE Priority: 0: Disable Rule, 1~7: Priority Setting (7 has the highest priority)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_PRIORITY_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_PRIORITY_MASK 0x70000000                // CR_BAND0_HEMU_RULE1_PRIORITY[30..28]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_PRIORITY_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_UDL_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_UDL_EN_MASK 0x04000000                // CR_BAND0_HEMU_RULE1_UDL_EN[26]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_UDL_EN_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_BSS_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_BSS_EN_MASK 0x02000000                // CR_BAND0_HEMU_RULE1_BSS_EN[25]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_BSS_EN_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_AID_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_AID_EN_MASK 0x01000000                // CR_BAND0_HEMU_RULE1_AID_EN[24]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_AID_EN_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_UDL_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_UDL_MASK 0x00400000                // CR_BAND0_HEMU_RULE1_UDL[22]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_UDL_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_BSS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_BSS_MASK 0x003F0000                // CR_BAND0_HEMU_RULE1_BSS[21..16]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_BSS_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_AID_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_AID_MASK 0x000007FF                // CR_BAND0_HEMU_RULE1_AID[10..0]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE1_CR_BAND0_HEMU_RULE1_AID_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HEMU_RULE2 (0x82000000 + 0x1154)---

    CR_BAND0_HEMU_RULE2_AID[10..0] - (RW) HEMU RULE AID:  AID field are used to address the STAs in this field.
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND0_HEMU_RULE2_BSS[21..16] - (RW) HEMU RULE BSS_COLOR: The BSS Color field is an identifier of the BSS
    CR_BAND0_HEMU_RULE2_UDL[22]  - (RW) HEMU RULE UL/DL: Set to 0 for DL, Set to 1 for UL
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE2_AID_EN[24] - (RW) HEMU RULE AID Enable: 0 Disable, 1:Enable
    CR_BAND0_HEMU_RULE2_BSS_EN[25] - (RW) HEMU RULE BSS_COLOR Enable: 0: Disable, 1: Enable
    CR_BAND0_HEMU_RULE2_UDL_EN[26] - (RW) HEMU RULE UL/DL Enable: 0 Disable, 1:Enable
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE2_PRIORITY[30..28] - (RW) HEMU RULE Priority: 0: Disable Rule, 1~7: Priority Setting (7 has the highest priority)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_PRIORITY_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_PRIORITY_MASK 0x70000000                // CR_BAND0_HEMU_RULE2_PRIORITY[30..28]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_PRIORITY_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_UDL_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_UDL_EN_MASK 0x04000000                // CR_BAND0_HEMU_RULE2_UDL_EN[26]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_UDL_EN_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_BSS_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_BSS_EN_MASK 0x02000000                // CR_BAND0_HEMU_RULE2_BSS_EN[25]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_BSS_EN_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_AID_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_AID_EN_MASK 0x01000000                // CR_BAND0_HEMU_RULE2_AID_EN[24]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_AID_EN_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_UDL_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_UDL_MASK 0x00400000                // CR_BAND0_HEMU_RULE2_UDL[22]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_UDL_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_BSS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_BSS_MASK 0x003F0000                // CR_BAND0_HEMU_RULE2_BSS[21..16]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_BSS_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_AID_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_AID_MASK 0x000007FF                // CR_BAND0_HEMU_RULE2_AID[10..0]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE2_CR_BAND0_HEMU_RULE2_AID_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HEMU_RULE3 (0x82000000 + 0x1158)---

    CR_BAND0_HEMU_RULE3_AID[10..0] - (RW) HEMU RULE AID:  AID field are used to address the STAs in this field.
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND0_HEMU_RULE3_BSS[21..16] - (RW) HEMU RULE BSS_COLOR: The BSS Color field is an identifier of the BSS
    CR_BAND0_HEMU_RULE3_UDL[22]  - (RW) HEMU RULE UL/DL: Set to 0 for DL, Set to 1 for UL
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE3_AID_EN[24] - (RW) HEMU RULE AID Enable: 0 Disable, 1:Enable
    CR_BAND0_HEMU_RULE3_BSS_EN[25] - (RW) HEMU RULE BSS_COLOR Enable: 0: Disable, 1: Enable
    CR_BAND0_HEMU_RULE3_UDL_EN[26] - (RW) HEMU RULE UL/DL Enable: 0 Disable, 1:Enable
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE3_PRIORITY[30..28] - (RW) HEMU RULE Priority: 0: Disable Rule, 1~7: Priority Setting (7 has the highest priority)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_PRIORITY_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_PRIORITY_MASK 0x70000000                // CR_BAND0_HEMU_RULE3_PRIORITY[30..28]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_PRIORITY_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_UDL_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_UDL_EN_MASK 0x04000000                // CR_BAND0_HEMU_RULE3_UDL_EN[26]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_UDL_EN_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_BSS_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_BSS_EN_MASK 0x02000000                // CR_BAND0_HEMU_RULE3_BSS_EN[25]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_BSS_EN_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_AID_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_AID_EN_MASK 0x01000000                // CR_BAND0_HEMU_RULE3_AID_EN[24]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_AID_EN_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_UDL_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_UDL_MASK 0x00400000                // CR_BAND0_HEMU_RULE3_UDL[22]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_UDL_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_BSS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_BSS_MASK 0x003F0000                // CR_BAND0_HEMU_RULE3_BSS[21..16]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_BSS_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_AID_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_AID_MASK 0x000007FF                // CR_BAND0_HEMU_RULE3_AID[10..0]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE3_CR_BAND0_HEMU_RULE3_AID_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HEMU_RULE4 (0x82000000 + 0x115C)---

    CR_BAND0_HEMU_RULE4_AID[10..0] - (RW) HEMU RULE AID:  AID field are used to address the STAs in this field.
    RESERVED11[15..11]           - (RO) Reserved bits
    CR_BAND0_HEMU_RULE4_BSS[21..16] - (RW) HEMU RULE BSS_COLOR: The BSS Color field is an identifier of the BSS
    CR_BAND0_HEMU_RULE4_UDL[22]  - (RW) HEMU RULE UL/DL: Set to 0 for DL, Set to 1 for UL
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE4_AID_EN[24] - (RW) HEMU RULE AID Enable: 0 Disable, 1:Enable
    CR_BAND0_HEMU_RULE4_BSS_EN[25] - (RW) HEMU RULE BSS_COLOR Enable: 0: Disable, 1: Enable
    CR_BAND0_HEMU_RULE4_UDL_EN[26] - (RW) HEMU RULE UL/DL Enable: 0 Disable, 1:Enable
    RESERVED27[27]               - (RO) Reserved bits
    CR_BAND0_HEMU_RULE4_PRIORITY[30..28] - (RW) HEMU RULE Priority: 0: Disable Rule, 1~7: Priority Setting (7 has the highest priority)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_PRIORITY_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_PRIORITY_MASK 0x70000000                // CR_BAND0_HEMU_RULE4_PRIORITY[30..28]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_PRIORITY_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_UDL_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_UDL_EN_MASK 0x04000000                // CR_BAND0_HEMU_RULE4_UDL_EN[26]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_UDL_EN_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_BSS_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_BSS_EN_MASK 0x02000000                // CR_BAND0_HEMU_RULE4_BSS_EN[25]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_BSS_EN_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_AID_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_AID_EN_MASK 0x01000000                // CR_BAND0_HEMU_RULE4_AID_EN[24]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_AID_EN_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_UDL_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_UDL_MASK 0x00400000                // CR_BAND0_HEMU_RULE4_UDL[22]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_UDL_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_BSS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_BSS_MASK 0x003F0000                // CR_BAND0_HEMU_RULE4_BSS[21..16]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_BSS_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_AID_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_AID_MASK 0x000007FF                // CR_BAND0_HEMU_RULE4_AID[10..0]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_RULE4_CR_BAND0_HEMU_RULE4_AID_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HEMU_DBG_USER (0x82000000 + 0x1160)---

    CR_BAND0_HEMU_USER_FIELD_IDX[6..0] - (RW) HEMU SIGB DBG USER IDEX
    RESERVED7[7]                 - (RO) Reserved bits
    CR_BAND0_HEMU_USER_CC_IDX[8] - (RW) HEMU SIGB DBG USER CC
    RESERVED9[31..9]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_CR_BAND0_HEMU_USER_CC_IDX_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_CR_BAND0_HEMU_USER_CC_IDX_MASK 0x00000100                // CR_BAND0_HEMU_USER_CC_IDX[8]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_CR_BAND0_HEMU_USER_CC_IDX_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_CR_BAND0_HEMU_USER_FIELD_IDX_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_CR_BAND0_HEMU_USER_FIELD_IDX_MASK 0x0000007F                // CR_BAND0_HEMU_USER_FIELD_IDX[6..0]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_DBG_USER_CR_BAND0_HEMU_USER_FIELD_IDX_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS1 (0x82000000 + 0x1170)---

    RO_BAND0_HEMU_ALL_RU_NUM[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS1_RO_BAND0_HEMU_ALL_RU_NUM_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS1_RO_BAND0_HEMU_ALL_RU_NUM_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_ALL_RU_NUM[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS1_RO_BAND0_HEMU_ALL_RU_NUM_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS2 (0x82000000 + 0x1174)---

    RO_BAND0_HEMU_CC1_RU_COMMON[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS2_RO_BAND0_HEMU_CC1_RU_COMMON_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS2_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS2_RO_BAND0_HEMU_CC1_RU_COMMON_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_CC1_RU_COMMON[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS2_RO_BAND0_HEMU_CC1_RU_COMMON_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS3 (0x82000000 + 0x1178)---

    RO_BAND0_HEMU_CC1_USER_NUM[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS3_RO_BAND0_HEMU_CC1_USER_NUM_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS3_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS3_RO_BAND0_HEMU_CC1_USER_NUM_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_CC1_USER_NUM[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS3_RO_BAND0_HEMU_CC1_USER_NUM_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS4 (0x82000000 + 0x117C)---

    RO_BAND0_HEMU_CC2_RU_COMMON[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS4_RO_BAND0_HEMU_CC2_RU_COMMON_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS4_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS4_RO_BAND0_HEMU_CC2_RU_COMMON_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_CC2_RU_COMMON[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS4_RO_BAND0_HEMU_CC2_RU_COMMON_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS5 (0x82000000 + 0x1180)---

    RO_BAND0_HEMU_CC2_USER_NUM[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS5_RO_BAND0_HEMU_CC2_USER_NUM_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS5_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS5_RO_BAND0_HEMU_CC2_USER_NUM_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_CC2_USER_NUM[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS5_RO_BAND0_HEMU_CC2_USER_NUM_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS6 (0x82000000 + 0x1184)---

    RO_BAND0_HEMU_CC_USER_CNT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS6_RO_BAND0_HEMU_CC_USER_CNT_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS6_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS6_RO_BAND0_HEMU_CC_USER_CNT_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_CC_USER_CNT[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS6_RO_BAND0_HEMU_CC_USER_CNT_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS7 (0x82000000 + 0x1188)---

    RO_BAND0_HEMU_DBG_USER[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS7_RO_BAND0_HEMU_DBG_USER_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS7_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS7_RO_BAND0_HEMU_DBG_USER_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_DBG_USER[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS7_RO_BAND0_HEMU_DBG_USER_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS8 (0x82000000 + 0x118C)---

    RO_BAND0_HEMU_HIGH_PRIORITY_INFO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS8_RO_BAND0_HEMU_HIGH_PRIORITY_INFO_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS8_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS8_RO_BAND0_HEMU_HIGH_PRIORITY_INFO_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_HIGH_PRIORITY_INFO[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS8_RO_BAND0_HEMU_HIGH_PRIORITY_INFO_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS9 (0x82000000 + 0x1190)---

    RO_BAND0_HEMU_MU_MIMO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS9_RO_BAND0_HEMU_MU_MIMO_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS9_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS9_RO_BAND0_HEMU_MU_MIMO_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_MU_MIMO[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS9_RO_BAND0_HEMU_MU_MIMO_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS10 (0x82000000 + 0x1194)---

    RO_BAND0_HEMU_RULE_HIT_INFO[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS10_RO_BAND0_HEMU_RULE_HIT_INFO_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS10_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS10_RO_BAND0_HEMU_RULE_HIT_INFO_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_RULE_HIT_INFO[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS10_RO_BAND0_HEMU_RULE_HIT_INFO_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HEMU_SIGB_STS11 (0x82000000 + 0x1198)---

    RO_BAND0_HEMU_USER_FIELD[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS11_RO_BAND0_HEMU_USER_FIELD_ADDR WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS11_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS11_RO_BAND0_HEMU_USER_FIELD_MASK 0xFFFFFFFF                // RO_BAND0_HEMU_USER_FIELD[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_HEMU_SIGB_STS11_RO_BAND0_HEMU_USER_FIELD_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HEMU_MANUAL1 (0x82000000 + 0x11A0)---

    CR_BAND0_HE_RU_BAND_IDX[2..0] - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_SIZE_IDX[7..3] - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_NSTS[10..8]   - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_TXBF[11]      - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_MCS[15..12]   - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_DCM[16]       - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_CODING[17]    - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_IS_MUMIMO[18] - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_NSTS_POS[26..19] - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_ALL_NSTS[30..27] - (RW) HEMU Manual value setting
    CR_BAND0_HE_RU_MANUAL[31]    - (RW) HEMU MANUAL MODE

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_MANUAL_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_MANUAL_MASK 0x80000000                // CR_BAND0_HE_RU_MANUAL[31]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_MANUAL_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_ALL_NSTS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_ALL_NSTS_MASK 0x78000000                // CR_BAND0_HE_RU_ALL_NSTS[30..27]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_ALL_NSTS_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_NSTS_POS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_NSTS_POS_MASK 0x07F80000                // CR_BAND0_HE_RU_NSTS_POS[26..19]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_NSTS_POS_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_IS_MUMIMO_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_IS_MUMIMO_MASK 0x00040000                // CR_BAND0_HE_RU_IS_MUMIMO[18]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_IS_MUMIMO_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_CODING_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_CODING_MASK 0x00020000                // CR_BAND0_HE_RU_CODING[17]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_CODING_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_DCM_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_DCM_MASK 0x00010000                // CR_BAND0_HE_RU_DCM[16]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_DCM_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_MCS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_MCS_MASK 0x0000F000                // CR_BAND0_HE_RU_MCS[15..12]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_MCS_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_TXBF_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_TXBF_MASK 0x00000800                // CR_BAND0_HE_RU_TXBF[11]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_TXBF_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_NSTS_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_NSTS_MASK 0x00000700                // CR_BAND0_HE_RU_NSTS[10..8]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_NSTS_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_SIZE_IDX_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_SIZE_IDX_MASK 0x000000F8                // CR_BAND0_HE_RU_SIZE_IDX[7..3]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_SIZE_IDX_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_BAND_IDX_ADDR WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_BAND_IDX_MASK 0x00000007                // CR_BAND0_HE_RU_BAND_IDX[2..0]
#define WF_PHYRX_CTRL_CR_BAND0_HEMU_MANUAL1_CR_BAND0_HE_RU_BAND_IDX_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIGA_MANUAL1 (0x82000000 + 0x11A8)---

    CR_BAND0_HESIGA_MANUAL_A1[25..0] - (RW) HESIGA Manual Value A1 (B25-B0)
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_BAND0_HESIGA_MANUAL_MODE[28] - (RW) HESIGA Manual Mode
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_CR_BAND0_HESIGA_MANUAL_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_CR_BAND0_HESIGA_MANUAL_MODE_MASK 0x10000000                // CR_BAND0_HESIGA_MANUAL_MODE[28]
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_CR_BAND0_HESIGA_MANUAL_MODE_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_CR_BAND0_HESIGA_MANUAL_A1_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_CR_BAND0_HESIGA_MANUAL_A1_MASK 0x03FFFFFF                // CR_BAND0_HESIGA_MANUAL_A1[25..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL1_CR_BAND0_HESIGA_MANUAL_A1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_HESIGA_MANUAL2 (0x82000000 + 0x11AC)---

    CR_BAND0_HESIGA_MANUAL_A2[15..0] - (RW) HESIGA Manual Value A2 (B15-B0)
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL2_CR_BAND0_HESIGA_MANUAL_A2_ADDR WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL2_CR_BAND0_HESIGA_MANUAL_A2_MASK 0x0000FFFF                // CR_BAND0_HESIGA_MANUAL_A2[15..0]
#define WF_PHYRX_CTRL_CR_BAND0_HESIGA_MANUAL2_CR_BAND0_HESIGA_MANUAL_A2_SHFT 0

/* =====================================================================================

  ---RO_BAND0_LG_SIG (0x82000000 + 0x11B0)---

    RO_BAND0_LG_SIG[17..0]       - (RO) LGSIG
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_LG_SIG_RO_BAND0_LG_SIG_ADDR     WF_PHYRX_CTRL_RO_BAND0_LG_SIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_LG_SIG_RO_BAND0_LG_SIG_MASK     0x0003FFFF                // RO_BAND0_LG_SIG[17..0]
#define WF_PHYRX_CTRL_RO_BAND0_LG_SIG_RO_BAND0_LG_SIG_SHFT     0

/* =====================================================================================

  ---RO_BAND0_RL_SIG (0x82000000 + 0x11B4)---

    RO_BAND0_RL_SIG[17..0]       - (RO) RLSIG
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RL_SIG_RO_BAND0_RL_SIG_ADDR     WF_PHYRX_CTRL_RO_BAND0_RL_SIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RL_SIG_RO_BAND0_RL_SIG_MASK     0x0003FFFF                // RO_BAND0_RL_SIG[17..0]
#define WF_PHYRX_CTRL_RO_BAND0_RL_SIG_RO_BAND0_RL_SIG_SHFT     0

/* =====================================================================================

  ---RO_BAND0_HESIGA_A1 (0x82000000 + 0x11B8)---

    RO_BAND0_HESIGA_A1[25..0]    - (RO) HESIGA A1 (B25-B0)
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A1_RO_BAND0_HESIGA_A1_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIGA_A1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A1_RO_BAND0_HESIGA_A1_MASK 0x03FFFFFF                // RO_BAND0_HESIGA_A1[25..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A1_RO_BAND0_HESIGA_A1_SHFT 0

/* =====================================================================================

  ---RO_BAND0_HESIGA_A2 (0x82000000 + 0x11BC)---

    RO_BAND0_HESIGA_A2[15..0]    - (RO) HESIGA A2 (B15-B0)
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A2_RO_BAND0_HESIGA_A2_ADDR WF_PHYRX_CTRL_RO_BAND0_HESIGA_A2_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A2_RO_BAND0_HESIGA_A2_MASK 0x0000FFFF                // RO_BAND0_HESIGA_A2[15..0]
#define WF_PHYRX_CTRL_RO_BAND0_HESIGA_A2_RO_BAND0_HESIGA_A2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_CTRL_0 (0x82000000 + 0x1900)---

    CR_BAND0_BBRX_ENA[7..0]      - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND0_BBRX_OFF[15..8]     - (RW) [DE] BBP PHYINTF RX control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BAND0_DIS_ST_ERR[30]      - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND0_DIS_EVM[31]         - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_DIS_EVM_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_DIS_EVM_MASK 0x80000000                // CR_BAND0_DIS_EVM[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_DIS_EVM_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_DIS_ST_ERR_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_DIS_ST_ERR_MASK 0x40000000                // CR_BAND0_DIS_ST_ERR[30]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_DIS_ST_ERR_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_BBRX_OFF_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_BBRX_OFF_MASK 0x0000FF00                // CR_BAND0_BBRX_OFF[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_BBRX_OFF_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_BBRX_ENA_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_BBRX_ENA_MASK 0x000000FF                // CR_BAND0_BBRX_ENA[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_0_CR_BAND0_BBRX_ENA_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_CTRL_1 (0x82000000 + 0x1904)---

    CR_BAND0_IPI_EN_CTRL[2..0]   - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND0_RPI_EN_CTRL[5..3]   - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND0_RDD_EN_CTRL[8..6]   - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND0_STSCNT_EN_CTRL[11..9] - (RW) [DE] BBP PHYINTF RX control CR
    RESERVED12[29..12]           - (RO) Reserved bits
    CR_BAND0_PHYINTF_MDRDY_MASK[31..30] - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_PHYINTF_MDRDY_MASK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_PHYINTF_MDRDY_MASK_MASK 0xC0000000                // CR_BAND0_PHYINTF_MDRDY_MASK[31..30]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_PHYINTF_MDRDY_MASK_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_STSCNT_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_STSCNT_EN_CTRL_MASK 0x00000E00                // CR_BAND0_STSCNT_EN_CTRL[11..9]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_STSCNT_EN_CTRL_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_RDD_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_RDD_EN_CTRL_MASK 0x000001C0                // CR_BAND0_RDD_EN_CTRL[8..6]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_RDD_EN_CTRL_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_RPI_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_RPI_EN_CTRL_MASK 0x00000038                // CR_BAND0_RPI_EN_CTRL[5..3]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_RPI_EN_CTRL_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_IPI_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_IPI_EN_CTRL_MASK 0x00000007                // CR_BAND0_IPI_EN_CTRL[2..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_1_CR_BAND0_IPI_EN_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_CTRL_2 (0x82000000 + 0x1910)---

    CR_BAND0_RXAFT_SEL_0[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_2_CR_BAND0_RXAFT_SEL_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_2_CR_BAND0_RXAFT_SEL_0_MASK 0xFFFFFFFF                // CR_BAND0_RXAFT_SEL_0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_2_CR_BAND0_RXAFT_SEL_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_CTRL_3 (0x82000000 + 0x1914)---

    CR_BAND0_RXAFT_SEL_1[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_3_CR_BAND0_RXAFT_SEL_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_3_CR_BAND0_RXAFT_SEL_1_MASK 0xFFFFFFFF                // CR_BAND0_RXAFT_SEL_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_3_CR_BAND0_RXAFT_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_CTRL_4 (0x82000000 + 0x1918)---

    CR_BAND0_RXAFT_SEL_2[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_4_CR_BAND0_RXAFT_SEL_2_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_4_CR_BAND0_RXAFT_SEL_2_MASK 0xFFFFFFFF                // CR_BAND0_RXAFT_SEL_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_4_CR_BAND0_RXAFT_SEL_2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_CTRL_5 (0x82000000 + 0x191C)---

    CR_BAND0_RXAFT_SEL_3[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_5_CR_BAND0_RXAFT_SEL_3_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_5_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_5_CR_BAND0_RXAFT_SEL_3_MASK 0xFFFFFFFF                // CR_BAND0_RXAFT_SEL_3[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_CTRL_5_CR_BAND0_RXAFT_SEL_3_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_TEST_MODE_0 (0x82000000 + 0x1920)---

    CR_BAND0_TEST_OUT[31..0]     - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_TEST_MODE_0_CR_BAND0_TEST_OUT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_TEST_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_TEST_MODE_0_CR_BAND0_TEST_OUT_MASK 0xFFFFFFFF                // CR_BAND0_TEST_OUT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_TEST_MODE_0_CR_BAND0_TEST_OUT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_MANUAL_MODE_0 (0x82000000 + 0x1928)---

    RESERVED0[29..0]             - (RO) Reserved bits
    CR_BAND0_PHYINTF_RX_MANUAL_ON[30] - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND0_PHYINTF_RX_MANUAL_MODE[31] - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_CR_BAND0_PHYINTF_RX_MANUAL_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_CR_BAND0_PHYINTF_RX_MANUAL_MODE_MASK 0x80000000                // CR_BAND0_PHYINTF_RX_MANUAL_MODE[31]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_CR_BAND0_PHYINTF_RX_MANUAL_MODE_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_CR_BAND0_PHYINTF_RX_MANUAL_ON_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_CR_BAND0_PHYINTF_RX_MANUAL_ON_MASK 0x40000000                // CR_BAND0_PHYINTF_RX_MANUAL_ON[30]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_MANUAL_MODE_0_CR_BAND0_PHYINTF_RX_MANUAL_ON_SHFT 30

/* =====================================================================================

  ---CR_BAND0_RXV_SEL_0 (0x82000000 + 0x19B0)---

    CR_BAND0_RXV_RXTD_SEL[1..0]  - (RW) [DE] BBP control CR
    CR_BAND0_RXV_WBRSSI_SEL[3..2] - (RW) [DE] BBP control CR
    CR_BAND0_RXV_IBRSSI_SEL[5..4] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RXV_RCPI_MODE[7..6] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RXV_LTF_SNR_EN[8] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RXV_SEL_G0[10..9] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RXV_SEL_G1[15..11] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RXV_SEL_G2[20..16] - (RW) [DE] BBP control CR
    CR_BAND0_RXV_DBG_SEL[24..21] - (RW) [DE] BBP control CR
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_DBG_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_DBG_SEL_MASK 0x01E00000                // CR_BAND0_RXV_DBG_SEL[24..21]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_DBG_SEL_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G2_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G2_MASK 0x001F0000                // CR_BAND0_PHYMUX_RXV_SEL_G2[20..16]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G2_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G1_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G1_MASK 0x0000F800                // CR_BAND0_PHYMUX_RXV_SEL_G1[15..11]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G1_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G0_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G0_MASK 0x00000600                // CR_BAND0_PHYMUX_RXV_SEL_G0[10..9]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_SEL_G0_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_LTF_SNR_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_LTF_SNR_EN_MASK 0x00000100                // CR_BAND0_PHYMUX_RXV_LTF_SNR_EN[8]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_LTF_SNR_EN_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_RCPI_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_RCPI_MODE_MASK 0x000000C0                // CR_BAND0_PHYMUX_RXV_RCPI_MODE[7..6]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_PHYMUX_RXV_RCPI_MODE_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_IBRSSI_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_IBRSSI_SEL_MASK 0x00000030                // CR_BAND0_RXV_IBRSSI_SEL[5..4]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_IBRSSI_SEL_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_WBRSSI_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_WBRSSI_SEL_MASK 0x0000000C                // CR_BAND0_RXV_WBRSSI_SEL[3..2]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_WBRSSI_SEL_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_RXTD_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_RXTD_SEL_MASK 0x00000003                // CR_BAND0_RXV_RXTD_SEL[1..0]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_0_CR_BAND0_RXV_RXTD_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_RXV_SEL_1 (0x82000000 + 0x19B4)---

    CR_BAND0_RXV_VEC3_SEL[7..0]  - (RW) [DE] BBP control CR
    CR_BAND0_RXV_VEC2_SEL[15..8] - (RW) [DE] BBP control CR
    CR_BAND0_RXV_VEC1_SEL[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC1_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC1_SEL_MASK 0x00FF0000                // CR_BAND0_RXV_VEC1_SEL[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC1_SEL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC2_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC2_SEL_MASK 0x0000FF00                // CR_BAND0_RXV_VEC2_SEL[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC2_SEL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC3_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC3_SEL_MASK 0x000000FF                // CR_BAND0_RXV_VEC3_SEL[7..0]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_1_CR_BAND0_RXV_VEC3_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_RXV_SEL_2 (0x82000000 + 0x19B8)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND0_RXV_VEC6_SEL[15..8] - (RW) [DE] BBP control CR
    CR_BAND0_RXV_VEC5_SEL[23..16] - (RW) [DE] BBP control CR
    CR_BAND0_RXV_VEC4_SEL[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC4_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC4_SEL_MASK 0xFF000000                // CR_BAND0_RXV_VEC4_SEL[31..24]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC4_SEL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC5_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC5_SEL_MASK 0x00FF0000                // CR_BAND0_RXV_VEC5_SEL[23..16]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC5_SEL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC6_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC6_SEL_MASK 0x0000FF00                // CR_BAND0_RXV_VEC6_SEL[15..8]
#define WF_PHYRX_CTRL_CR_BAND0_RXV_SEL_2_CR_BAND0_RXV_VEC6_SEL_SHFT 8

/* =====================================================================================

  ---CR_BAND0_RXD_CTRL (0x82000000 + 0x19BC)---

    CR_BAND0_PHYMUX_RXD_DLY[4..0] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RXD2RXV_DLY[9..5] - (RW) [DE] BBP control CR
    RESERVED10[15..10]           - (RO) Reserved bits
    CR_PHYMUX_RXANT_MAPPING[16]  - (RW) [DE] BBP control CR
    RESERVED17[31..17]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_PHYMUX_RXANT_MAPPING_ADDR WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_PHYMUX_RXANT_MAPPING_MASK 0x00010000                // CR_PHYMUX_RXANT_MAPPING[16]
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_PHYMUX_RXANT_MAPPING_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_BAND0_PHYMUX_RXD2RXV_DLY_ADDR WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_BAND0_PHYMUX_RXD2RXV_DLY_MASK 0x000003E0                // CR_BAND0_PHYMUX_RXD2RXV_DLY[9..5]
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_BAND0_PHYMUX_RXD2RXV_DLY_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_BAND0_PHYMUX_RXD_DLY_ADDR WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_BAND0_PHYMUX_RXD_DLY_MASK 0x0000001F                // CR_BAND0_PHYMUX_RXD_DLY[4..0]
#define WF_PHYRX_CTRL_CR_BAND0_RXD_CTRL_CR_BAND0_PHYMUX_RXD_DLY_SHFT 0

/* =====================================================================================

  ---CR_BAND0_MANUAL_PHYMUX_RX_MODE_0 (0x82000000 + 0x19C0)---

    CR_BAND0_PHYMUX_RX_MANUAL_ON[0] - (RW) [DE] BBP control CR
    CR_BAND0_PHYMUX_RX_MANUAL_MODE[1] - (RW) [DE] BBP control CR
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_CR_BAND0_PHYMUX_RX_MANUAL_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_CR_BAND0_PHYMUX_RX_MANUAL_MODE_MASK 0x00000002                // CR_BAND0_PHYMUX_RX_MANUAL_MODE[1]
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_CR_BAND0_PHYMUX_RX_MANUAL_MODE_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_CR_BAND0_PHYMUX_RX_MANUAL_ON_ADDR WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_CR_BAND0_PHYMUX_RX_MANUAL_ON_MASK 0x00000001                // CR_BAND0_PHYMUX_RX_MANUAL_ON[0]
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_0_CR_BAND0_PHYMUX_RX_MANUAL_ON_SHFT 0

/* =====================================================================================

  ---CR_BAND0_MANUAL_PHYMUX_RX_MODE_1 (0x82000000 + 0x19C4)---

    CR_BAND0_TEST_RXD[31..0]     - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_1_CR_BAND0_TEST_RXD_ADDR WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_1_CR_BAND0_TEST_RXD_MASK 0xFFFFFFFF                // CR_BAND0_TEST_RXD[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_MANUAL_PHYMUX_RX_MODE_1_CR_BAND0_TEST_RXD_SHFT 0

/* =====================================================================================

  ---RO_BAND0_RXV_0 (0x82000000 + 0x19D0)---

    RO_BAND0_RXV_AFT1[31..0]     - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_0_RO_BAND0_RXV_AFT1_ADDR    WF_PHYRX_CTRL_RO_BAND0_RXV_0_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_0_RO_BAND0_RXV_AFT1_MASK    0xFFFFFFFF                // RO_BAND0_RXV_AFT1[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_0_RO_BAND0_RXV_AFT1_SHFT    0

/* =====================================================================================

  ---RO_BAND0_RXV_1 (0x82000000 + 0x19D4)---

    RO_BAND0_RXV_AFT2[31..0]     - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_1_RO_BAND0_RXV_AFT2_ADDR    WF_PHYRX_CTRL_RO_BAND0_RXV_1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_1_RO_BAND0_RXV_AFT2_MASK    0xFFFFFFFF                // RO_BAND0_RXV_AFT2[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_1_RO_BAND0_RXV_AFT2_SHFT    0

/* =====================================================================================

  ---RO_BAND0_RXV_2 (0x82000000 + 0x19D8)---

    RO_BAND0_RXV_AFT3[31..0]     - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_2_RO_BAND0_RXV_AFT3_ADDR    WF_PHYRX_CTRL_RO_BAND0_RXV_2_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_2_RO_BAND0_RXV_AFT3_MASK    0xFFFFFFFF                // RO_BAND0_RXV_AFT3[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_2_RO_BAND0_RXV_AFT3_SHFT    0

/* =====================================================================================

  ---RO_BAND0_RXV_3 (0x82000000 + 0x19DC)---

    RO_BAND0_RXV1[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_3_RO_BAND0_RXV1_ADDR        WF_PHYRX_CTRL_RO_BAND0_RXV_3_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_3_RO_BAND0_RXV1_MASK        0xFFFFFFFF                // RO_BAND0_RXV1[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_3_RO_BAND0_RXV1_SHFT        0

/* =====================================================================================

  ---RO_BAND0_RXV_4 (0x82000000 + 0x19E0)---

    RO_BAND0_RXV2[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_4_RO_BAND0_RXV2_ADDR        WF_PHYRX_CTRL_RO_BAND0_RXV_4_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_4_RO_BAND0_RXV2_MASK        0xFFFFFFFF                // RO_BAND0_RXV2[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_4_RO_BAND0_RXV2_SHFT        0

/* =====================================================================================

  ---RO_BAND0_RXV_5 (0x82000000 + 0x19E4)---

    RO_BAND0_RXV3[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_5_RO_BAND0_RXV3_ADDR        WF_PHYRX_CTRL_RO_BAND0_RXV_5_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_5_RO_BAND0_RXV3_MASK        0xFFFFFFFF                // RO_BAND0_RXV3[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_5_RO_BAND0_RXV3_SHFT        0

/* =====================================================================================

  ---RO_BAND0_RXV_6 (0x82000000 + 0x19E8)---

    RO_BAND0_RXV4[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_6_RO_BAND0_RXV4_ADDR        WF_PHYRX_CTRL_RO_BAND0_RXV_6_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_6_RO_BAND0_RXV4_MASK        0xFFFFFFFF                // RO_BAND0_RXV4[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_6_RO_BAND0_RXV4_SHFT        0

/* =====================================================================================

  ---RO_BAND0_RXV_7 (0x82000000 + 0x19EC)---

    RO_BAND0_RXV5[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_7_RO_BAND0_RXV5_ADDR        WF_PHYRX_CTRL_RO_BAND0_RXV_7_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_7_RO_BAND0_RXV5_MASK        0xFFFFFFFF                // RO_BAND0_RXV5[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_7_RO_BAND0_RXV5_SHFT        0

/* =====================================================================================

  ---RO_BAND0_RXV_8 (0x82000000 + 0x19F0)---

    RO_BAND0_RXV6[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_RXV_8_RO_BAND0_RXV6_ADDR        WF_PHYRX_CTRL_RO_BAND0_RXV_8_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_RXV_8_RO_BAND0_RXV6_MASK        0xFFFFFFFF                // RO_BAND0_RXV6[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_RXV_8_RO_BAND0_RXV6_SHFT        0

/* =====================================================================================

  ---CR_COMMON_PHYMUX_2 (0x82000000 + 0x19F4)---

    CR_TXLEN_VEC_CNT[2..0]       - (RW) [DE] BBP control CR
    RESERVED3[3]                 - (RO) Reserved bits
    CR_TXON_VEC_CNT[6..4]        - (RW) [DE] BBP control CR
    RESERVED7[7]                 - (RO) Reserved bits
    CR_TXPE_VEC_CNT[10..8]       - (RW) [DE] BBP control CR
    CR_RX_MMPS_TYP_SEL[11]       - (RW) [DE] BBP control CR
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_RX_MMPS_TYP_SEL_ADDR WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_ADDR
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_RX_MMPS_TYP_SEL_MASK 0x00000800                // CR_RX_MMPS_TYP_SEL[11]
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_RX_MMPS_TYP_SEL_SHFT 11
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXPE_VEC_CNT_ADDR  WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_ADDR
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXPE_VEC_CNT_MASK  0x00000700                // CR_TXPE_VEC_CNT[10..8]
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXPE_VEC_CNT_SHFT  8
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXON_VEC_CNT_ADDR  WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_ADDR
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXON_VEC_CNT_MASK  0x00000070                // CR_TXON_VEC_CNT[6..4]
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXON_VEC_CNT_SHFT  4
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXLEN_VEC_CNT_ADDR WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_ADDR
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXLEN_VEC_CNT_MASK 0x00000007                // CR_TXLEN_VEC_CNT[2..0]
#define WF_PHYRX_CTRL_CR_COMMON_PHYMUX_2_CR_TXLEN_VEC_CNT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYMUX_44 (0x82000000 + 0x19F8)---

    CR_TX_DYN_CBW_SWITCH_EN[0]   - (RW) [DE] BBP control CR
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_44_CR_TX_DYN_CBW_SWITCH_EN_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYMUX_44_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_44_CR_TX_DYN_CBW_SWITCH_EN_MASK 0x00000001                // CR_TX_DYN_CBW_SWITCH_EN[0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_44_CR_TX_DYN_CBW_SWITCH_EN_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYMUX_RSVD0 (0x82000000 + 0x1A00)---

    CR_BAND0_PHYMUX_RSVD0[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD0_CR_BAND0_PHYMUX_RSVD0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD0_CR_BAND0_PHYMUX_RSVD0_MASK 0xFFFFFFFF                // CR_BAND0_PHYMUX_RSVD0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD0_CR_BAND0_PHYMUX_RSVD0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYMUX_RSVD1 (0x82000000 + 0x1A04)---

    CR_BAND0_PHYMUX_RSVD1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD1_CR_BAND0_PHYMUX_RSVD1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD1_CR_BAND0_PHYMUX_RSVD1_MASK 0xFFFFFFFF                // CR_BAND0_PHYMUX_RSVD1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYMUX_RSVD1_CR_BAND0_PHYMUX_RSVD1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL (0x82000000 + 0x1A08)---

    CR_BAND0_PHYINTF_RX_USER_RXAFT_MON_SEL[3..0] - (RW) [DE] BBP PHYINTF RX RXV MON SEL
    CR_BAND0_PHYINTF_RX_USER_RXVEC_MON_SEL[7..4] - (RW) [DE] BBP PHYINTF RX RXV MON SEL
    CR_BAND0_PHYINTF_RX_COMM_RXAFT_MON_SEL[11..8] - (RW) [DE] BBP PHYINTF RX RXV MON SEL
    CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL[15..12] - (RW) [DE] BBP PHYINTF RX RXV MON SEL
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_MASK 0x0000F000                // CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL[15..12]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_COMM_RXAFT_MON_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_COMM_RXAFT_MON_SEL_MASK 0x00000F00                // CR_BAND0_PHYINTF_RX_COMM_RXAFT_MON_SEL[11..8]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_COMM_RXAFT_MON_SEL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_USER_RXVEC_MON_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_USER_RXVEC_MON_SEL_MASK 0x000000F0                // CR_BAND0_PHYINTF_RX_USER_RXVEC_MON_SEL[7..4]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_USER_RXVEC_MON_SEL_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_USER_RXAFT_MON_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_USER_RXAFT_MON_SEL_MASK 0x0000000F                // CR_BAND0_PHYINTF_RX_USER_RXAFT_MON_SEL[3..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_COMM_RXVEC_MON_SEL_CR_BAND0_PHYINTF_RX_USER_RXAFT_MON_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0 (0x82000000 + 0x1A0C)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1 (0x82000000 + 0x1A10)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2 (0x82000000 + 0x1A14)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3 (0x82000000 + 0x1A18)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_3_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4 (0x82000000 + 0x1A1C)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_4_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5 (0x82000000 + 0x1A20)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_5_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6 (0x82000000 + 0x1A24)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_6_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7 (0x82000000 + 0x1A28)---

    CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT0_RO_SEL_7_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL (0x82000000 + 0x1A2C)---

    CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL[1..0] - (RW) [DE] BBP PHYINTF RX WDT
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_MASK 0x00000003                // CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL[1..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT0_MODE_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_MASK (0x82000000 + 0x1A30)---

    CR_BAND0_PHYINTF_RX_WDT0_MASK[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MASK_CR_BAND0_PHYINTF_RX_WDT0_MASK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MASK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MASK_CR_BAND0_PHYINTF_RX_WDT0_MASK_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_MASK[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_MASK_CR_BAND0_PHYINTF_RX_WDT0_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_PAT (0x82000000 + 0x1A34)---

    CR_BAND0_PHYINTF_RX_WDT0_PAT[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_PAT_CR_BAND0_PHYINTF_RX_WDT0_PAT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_PAT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_PAT_CR_BAND0_PHYINTF_RX_WDT0_PAT_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_PAT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_PAT_CR_BAND0_PHYINTF_RX_WDT0_PAT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT0_CNT (0x82000000 + 0x1A38)---

    CR_BAND0_PHYINTF_RX_WDT0_CNT[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_CNT_CR_BAND0_PHYINTF_RX_WDT0_CNT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_CNT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_CNT_CR_BAND0_PHYINTF_RX_WDT0_CNT_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT0_CNT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT0_CNT_CR_BAND0_PHYINTF_RX_WDT0_CNT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0 (0x82000000 + 0x1A3C)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1 (0x82000000 + 0x1A40)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2 (0x82000000 + 0x1A44)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3 (0x82000000 + 0x1A48)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_3_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4 (0x82000000 + 0x1A4C)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_4_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5 (0x82000000 + 0x1A50)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_5_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6 (0x82000000 + 0x1A54)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_6_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7 (0x82000000 + 0x1A58)---

    CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT1_RO_SEL_7_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL (0x82000000 + 0x1A5C)---

    CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL[1..0] - (RW) [DE] BBP PHYINTF RX WDT
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_MASK 0x00000003                // CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL[1..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT1_MODE_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_MASK (0x82000000 + 0x1A60)---

    CR_BAND0_PHYINTF_RX_WDT1_MASK[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MASK_CR_BAND0_PHYINTF_RX_WDT1_MASK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MASK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MASK_CR_BAND0_PHYINTF_RX_WDT1_MASK_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_MASK[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_MASK_CR_BAND0_PHYINTF_RX_WDT1_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_PAT (0x82000000 + 0x1A64)---

    CR_BAND0_PHYINTF_RX_WDT1_PAT[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_PAT_CR_BAND0_PHYINTF_RX_WDT1_PAT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_PAT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_PAT_CR_BAND0_PHYINTF_RX_WDT1_PAT_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_PAT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_PAT_CR_BAND0_PHYINTF_RX_WDT1_PAT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT1_CNT (0x82000000 + 0x1A68)---

    CR_BAND0_PHYINTF_RX_WDT1_CNT[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_CNT_CR_BAND0_PHYINTF_RX_WDT1_CNT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_CNT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_CNT_CR_BAND0_PHYINTF_RX_WDT1_CNT_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT1_CNT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT1_CNT_CR_BAND0_PHYINTF_RX_WDT1_CNT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0 (0x82000000 + 0x1A6C)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1 (0x82000000 + 0x1A70)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2 (0x82000000 + 0x1A74)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3 (0x82000000 + 0x1A78)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_3_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4 (0x82000000 + 0x1A7C)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_4_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5 (0x82000000 + 0x1A80)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_5_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6 (0x82000000 + 0x1A84)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_6_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7 (0x82000000 + 0x1A88)---

    CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_CR_BAND0_PHYINTF_RX_WDT2_RO_SEL_7_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL (0x82000000 + 0x1A8C)---

    CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL[1..0] - (RW) [DE] BBP PHYINTF RX WDT
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_MASK 0x00000003                // CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL[1..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_CR_BAND0_PHYINTF_RX_WDT2_MODE_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_MASK (0x82000000 + 0x1A90)---

    CR_BAND0_PHYINTF_RX_WDT2_MASK[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MASK_CR_BAND0_PHYINTF_RX_WDT2_MASK_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MASK_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MASK_CR_BAND0_PHYINTF_RX_WDT2_MASK_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_MASK[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_MASK_CR_BAND0_PHYINTF_RX_WDT2_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_PAT (0x82000000 + 0x1A94)---

    CR_BAND0_PHYINTF_RX_WDT2_PAT[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_PAT_CR_BAND0_PHYINTF_RX_WDT2_PAT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_PAT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_PAT_CR_BAND0_PHYINTF_RX_WDT2_PAT_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_PAT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_PAT_CR_BAND0_PHYINTF_RX_WDT2_PAT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_WDT2_CNT (0x82000000 + 0x1A98)---

    CR_BAND0_PHYINTF_RX_WDT2_CNT[31..0] - (RW) [DE] BBP PHYINTF RX WDT

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_CNT_CR_BAND0_PHYINTF_RX_WDT2_CNT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_CNT_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_CNT_CR_BAND0_PHYINTF_RX_WDT2_CNT_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_WDT2_CNT[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_WDT2_CNT_CR_BAND0_PHYINTF_RX_WDT2_CNT_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0 (0x82000000 + 0x1A9C)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1 (0x82000000 + 0x1AA0)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2 (0x82000000 + 0x1AA4)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3 (0x82000000 + 0x1AA8)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_3_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4 (0x82000000 + 0x1AAC)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_4_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5 (0x82000000 + 0x1AB0)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_5_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6 (0x82000000 + 0x1AB4)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_6_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7 (0x82000000 + 0x1AB8)---

    CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7[31..0] - (RW) [DE] BBP PHYINTF RX FLAG

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_MASK 0xFFFFFFFF                // CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_CR_BAND0_PHYINTF_RX_FLAG_SIG_SEL_7_SHFT 0

/* =====================================================================================

  ---CR_BAND0_PHYINTF_RX_FLAG_SEL (0x82000000 + 0x1ABC)---

    CR_BAND0_PHYINTF_RX_FLAG_SHIFT_CNT[11..0] - (RW) [DE] BBP PHYINTF RX FLAG
    CR_BAND0_PHYINTF_RX_FLAG_SHIFT_MODE[15..12] - (RW) [DE] BBP PHYINTF RX FLAG
    CR_BAND0_PHYINTF_RX_FLAG_HSEL[17..16] - (RW) [DE] BBP PHYINTF RX FLAG
    CR_BAND0_PHYINTF_RX_FLAG_LSEL[19..18] - (RW) [DE] BBP PHYINTF RX FLAG
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_LSEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_LSEL_MASK 0x000C0000                // CR_BAND0_PHYINTF_RX_FLAG_LSEL[19..18]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_LSEL_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_HSEL_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_HSEL_MASK 0x00030000                // CR_BAND0_PHYINTF_RX_FLAG_HSEL[17..16]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_HSEL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_SHIFT_MODE_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_SHIFT_MODE_MASK 0x0000F000                // CR_BAND0_PHYINTF_RX_FLAG_SHIFT_MODE[15..12]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_SHIFT_MODE_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_SHIFT_CNT_ADDR WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_SHIFT_CNT_MASK 0x00000FFF                // CR_BAND0_PHYINTF_RX_FLAG_SHIFT_CNT[11..0]
#define WF_PHYRX_CTRL_CR_BAND0_PHYINTF_RX_FLAG_SEL_CR_BAND0_PHYINTF_RX_FLAG_SHIFT_CNT_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT (0x82000000 + 0x1B00)---

    RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_RO_BAND0_PHYINTF_RX_USER_CHAIN_VECCNT_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST (0x82000000 + 0x1B04)---

    RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_RO_BAND0_PHYINTF_RX_USER_CHAIN_RXST_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX (0x82000000 + 0x1B08)---

    RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_RO_BAND0_PHYINTF_RX_USER_CHAIN_MUX_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L (0x82000000 + 0x1B0C)---

    RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_L_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U (0x82000000 + 0x1B10)---

    RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXAFT_U_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L (0x82000000 + 0x1B14)---

    RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_L_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U (0x82000000 + 0x1B18)---

    RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_RO_BAND0_PHYINTF_RX_USER_FLAGMUX_RXVEC_U_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT (0x82000000 + 0x1B1C)---

    RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_RO_BAND0_PHYINTF_RX_COMM_CHAIN_VECCNT_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST (0x82000000 + 0x1B20)---

    RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_RO_BAND0_PHYINTF_RX_COMM_CHAIN_RXST_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX (0x82000000 + 0x1B24)---

    RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_RO_BAND0_PHYINTF_RX_COMM_CHAIN_MUX_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L (0x82000000 + 0x1B28)---

    RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_L_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U (0x82000000 + 0x1B2C)---

    RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXAFT_U_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L (0x82000000 + 0x1B30)---

    RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_L_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U (0x82000000 + 0x1B34)---

    RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_RO_BAND0_PHYINTF_RX_COMM_FLAGMUX_RXVEC_U_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_BBUID (0x82000000 + 0x1B38)---

    RO_BAND0_PHYINTF_RX_BBUID[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_BBUID_RO_BAND0_PHYINTF_RX_BBUID_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_BBUID_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_BBUID_RO_BAND0_PHYINTF_RX_BBUID_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_BBUID[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_BBUID_RO_BAND0_PHYINTF_RX_BBUID_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_PHYMACUID_0 (0x82000000 + 0x1B3C)---

    RO_BAND0_PHYINTF_RX_PHYMACUID_0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_0_RO_BAND0_PHYINTF_RX_PHYMACUID_0_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_0_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_0_RO_BAND0_PHYINTF_RX_PHYMACUID_0_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_PHYMACUID_0[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_0_RO_BAND0_PHYINTF_RX_PHYMACUID_0_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_PHYMACUID_1 (0x82000000 + 0x1B40)---

    RO_BAND0_PHYINTF_RX_PHYMACUID_1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_1_RO_BAND0_PHYINTF_RX_PHYMACUID_1_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_1_RO_BAND0_PHYINTF_RX_PHYMACUID_1_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_PHYMACUID_1[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PHYMACUID_1_RO_BAND0_PHYINTF_RX_PHYMACUID_1_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_MISC_0 (0x82000000 + 0x1B44)---

    RO_BAND0_PHYINTF_RX_MISC_0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_0_RO_BAND0_PHYINTF_RX_MISC_0_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_0_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_0_RO_BAND0_PHYINTF_RX_MISC_0_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_MISC_0[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_0_RO_BAND0_PHYINTF_RX_MISC_0_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_MISC_1 (0x82000000 + 0x1B48)---

    RO_BAND0_PHYINTF_RX_MISC_1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_1_RO_BAND0_PHYINTF_RX_MISC_1_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_1_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_1_RO_BAND0_PHYINTF_RX_MISC_1_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_MISC_1[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_MISC_1_RO_BAND0_PHYINTF_RX_MISC_1_SHFT 0

/* =====================================================================================

  ---RO_BAND0_PHYINTF_RX_PIPE (0x82000000 + 0x1B4C)---

    RO_BAND0_PHYINTF_RX_PIPE[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PIPE_RO_BAND0_PHYINTF_RX_PIPE_ADDR WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PIPE_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PIPE_RO_BAND0_PHYINTF_RX_PIPE_MASK 0xFFFFFFFF                // RO_BAND0_PHYINTF_RX_PIPE[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_PHYINTF_RX_PIPE_RO_BAND0_PHYINTF_RX_PIPE_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCK_MANU_MODE (0x82000000 + 0x2000)---

    CR_BAND1_PHYCK_MANU_MODE[23..0] - (RW) 0: HW Mode
                                     1: Manual Mode
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_MODE_CR_BAND1_PHYCK_MANU_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_MODE_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_MODE_CR_BAND1_PHYCK_MANU_MODE_MASK 0x00FFFFFF                // CR_BAND1_PHYCK_MANU_MODE[23..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_MODE_CR_BAND1_PHYCK_MANU_MODE_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCK_MANU_ENAB (0x82000000 + 0x2004)---

    CR_BAND1_PHYCK_MANU_ENAB[23..0] - (RW) 0: HW Mode
                                     1: Manual Mode
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_ENAB_CR_BAND1_PHYCK_MANU_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_ENAB_CR_BAND1_PHYCK_MANU_ENAB_MASK 0x00FFFFFF                // CR_BAND1_PHYCK_MANU_ENAB[23..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCK_MANU_ENAB_CR_BAND1_PHYCK_MANU_ENAB_SHFT 0

/* =====================================================================================

  ---CR_BAND1_OPOST_VARCK_TABLE (0x82000000 + 0x2010)---

    CR_BAND1_OPOST_VARCK_TAB[15..0] - (RW) 0: Down-sampling by half
                                     1: Maximum Speed
    CR_BAND1_MIMOD_VARCK_TAB[31..16] - (RW) 0: Down-sampling by half
                                     1: Maximum Speed

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_CR_BAND1_MIMOD_VARCK_TAB_ADDR WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_CR_BAND1_MIMOD_VARCK_TAB_MASK 0xFFFF0000                // CR_BAND1_MIMOD_VARCK_TAB[31..16]
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_CR_BAND1_MIMOD_VARCK_TAB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_CR_BAND1_OPOST_VARCK_TAB_ADDR WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_CR_BAND1_OPOST_VARCK_TAB_MASK 0x0000FFFF                // CR_BAND1_OPOST_VARCK_TAB[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_OPOST_VARCK_TABLE_CR_BAND1_OPOST_VARCK_TAB_SHFT 0

/* =====================================================================================

  ---CR_BAND1_OUTER_VARCK_TABLE (0x82000000 + 0x2014)---

    CR_BAND1_OUTER_VARCK_TAB[15..0] - (RW) 0: Down-sampling by half
                                     1: Maximum Speed
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_OUTER_VARCK_TABLE_CR_BAND1_OUTER_VARCK_TAB_ADDR WF_PHYRX_CTRL_CR_BAND1_OUTER_VARCK_TABLE_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_OUTER_VARCK_TABLE_CR_BAND1_OUTER_VARCK_TAB_MASK 0x0000FFFF                // CR_BAND1_OUTER_VARCK_TAB[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_OUTER_VARCK_TABLE_CR_BAND1_OUTER_VARCK_TAB_SHFT 0

/* =====================================================================================

  ---CR_BAND1_RST_CTRL (0x82000000 + 0x2020)---

    CR_BAND1_RFINTF_LOGRST[0]    - (RW) 1: Reset
    CR_BAND1_RXFE_LOGRST[1]      - (RW) 1: Reset
    CR_BAND1_RXTD_LOGRST[2]      - (RW) 1: Reset
    CR_BAND1_FFT_LOGRST[3]       - (RW) 1: Reset
    CR_BAND1_OPOST_LOGRST[4]     - (RW) 1: Reset
    CR_BAND1_PHYMISC_LOGRST[5]   - (RW) 1: Reset
    CR_BAND1_PHYMUX_LOGRST[6]    - (RW) 1: Reset
    CR_BAND1_PHYCTRL_LOGRST[7]   - (RW) 1: Reset
    CR_BAND1_TOAE_LOGRST[8]      - (RW) 1: Reset
    CR_BAND1_TOAE_CAL_LOGRST[9]  - (RW) 1: Reset
    CR_BAND1_RBIST_LOGRST[10]    - (RW) 1: Reset
    CR_BAND1_DPD_CAL_LOGRST[11]  - (RW) 1: Reset
    CR_BAND1_MAC2PHY_LOGRST[12]  - (RW) 1: Reset
    CR_BAND1_RDD_LOGRST[13]      - (RW) 1: Reset
    CR_BAND1_TSSI_LOGRST[14]     - (RW) 1: Reset
    CR_BAND1_TXFE_LOGRST[15]     - (RW) 1: Reset
    CR_BAND1_TXTD_LOGRST[16]     - (RW) 1: Reset
    CR_BAND1_TXFD_LOGRST[17]     - (RW) 1: Reset
    CR_OUTER_LOGRST[18]          - (RW) 1: Reset
    CR_CCKRX_LOGRST[19]          - (RW) 1: Reset
    CR_SVD_LOGRST[20]            - (RW) 4: Reset
    CR_MUTX_LOGRST[21]           - (RW) 3: Reset
    CR_PFMU_LOGRST[22]           - (RW) 2: Reset
    CR_BF_LOGRST[23]             - (RW) 1: Reset
    CR_BAND1_RSVD0_LOGRST[24]    - (RW) 1: Reset
    CR_BAND1_RSVD1_LOGRST[25]    - (RW) 1: Reset
    CR_BAND1_RSVD2_LOGRST[26]    - (RW) 1: Reset
    CR_BAND1_RSVD3_LOGRST[27]    - (RW) 1: Reset
    CR_BAND1_TXFD_CSRRST[28]     - (RW) 1: Reset
    CR_BAND1_RFINTF_CSRRST[29]   - (RW) 1: Reset
    CR_BAND1_RXFE_CSRRST[30]     - (RW) 1: Reset
    CR_CCKRX_CSRRST[31]          - (RW) 1: Reset

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_CCKRX_CSRRST_ADDR   WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_CCKRX_CSRRST_MASK   0x80000000                // CR_CCKRX_CSRRST[31]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_CCKRX_CSRRST_SHFT   31
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXFE_CSRRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXFE_CSRRST_MASK 0x40000000                // CR_BAND1_RXFE_CSRRST[30]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXFE_CSRRST_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RFINTF_CSRRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RFINTF_CSRRST_MASK 0x20000000                // CR_BAND1_RFINTF_CSRRST[29]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RFINTF_CSRRST_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFD_CSRRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFD_CSRRST_MASK 0x10000000                // CR_BAND1_TXFD_CSRRST[28]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFD_CSRRST_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD3_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD3_LOGRST_MASK 0x08000000                // CR_BAND1_RSVD3_LOGRST[27]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD3_LOGRST_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD2_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD2_LOGRST_MASK 0x04000000                // CR_BAND1_RSVD2_LOGRST[26]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD2_LOGRST_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD1_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD1_LOGRST_MASK 0x02000000                // CR_BAND1_RSVD1_LOGRST[25]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD1_LOGRST_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD0_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD0_LOGRST_MASK 0x01000000                // CR_BAND1_RSVD0_LOGRST[24]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RSVD0_LOGRST_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BF_LOGRST_ADDR      WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BF_LOGRST_MASK      0x00800000                // CR_BF_LOGRST[23]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BF_LOGRST_SHFT      23
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_PFMU_LOGRST_ADDR    WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_PFMU_LOGRST_MASK    0x00400000                // CR_PFMU_LOGRST[22]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_PFMU_LOGRST_SHFT    22
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_MUTX_LOGRST_ADDR    WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_MUTX_LOGRST_MASK    0x00200000                // CR_MUTX_LOGRST[21]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_MUTX_LOGRST_SHFT    21
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_SVD_LOGRST_ADDR     WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_SVD_LOGRST_MASK     0x00100000                // CR_SVD_LOGRST[20]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_SVD_LOGRST_SHFT     20
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_CCKRX_LOGRST_ADDR   WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_CCKRX_LOGRST_MASK   0x00080000                // CR_CCKRX_LOGRST[19]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_CCKRX_LOGRST_SHFT   19
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_OUTER_LOGRST_ADDR   WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_OUTER_LOGRST_MASK   0x00040000                // CR_OUTER_LOGRST[18]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_OUTER_LOGRST_SHFT   18
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFD_LOGRST_MASK 0x00020000                // CR_BAND1_TXFD_LOGRST[17]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFD_LOGRST_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXTD_LOGRST_MASK 0x00010000                // CR_BAND1_TXTD_LOGRST[16]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXTD_LOGRST_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFE_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFE_LOGRST_MASK 0x00008000                // CR_BAND1_TXFE_LOGRST[15]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TXFE_LOGRST_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TSSI_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TSSI_LOGRST_MASK 0x00004000                // CR_BAND1_TSSI_LOGRST[14]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TSSI_LOGRST_SHFT 14
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RDD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RDD_LOGRST_MASK 0x00002000                // CR_BAND1_RDD_LOGRST[13]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RDD_LOGRST_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_MAC2PHY_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_MAC2PHY_LOGRST_MASK 0x00001000                // CR_BAND1_MAC2PHY_LOGRST[12]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_MAC2PHY_LOGRST_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_DPD_CAL_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_DPD_CAL_LOGRST_MASK 0x00000800                // CR_BAND1_DPD_CAL_LOGRST[11]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_DPD_CAL_LOGRST_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RBIST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RBIST_LOGRST_MASK 0x00000400                // CR_BAND1_RBIST_LOGRST[10]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RBIST_LOGRST_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TOAE_CAL_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TOAE_CAL_LOGRST_MASK 0x00000200                // CR_BAND1_TOAE_CAL_LOGRST[9]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TOAE_CAL_LOGRST_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TOAE_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TOAE_LOGRST_MASK 0x00000100                // CR_BAND1_TOAE_LOGRST[8]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_TOAE_LOGRST_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYCTRL_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYCTRL_LOGRST_MASK 0x00000080                // CR_BAND1_PHYCTRL_LOGRST[7]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYCTRL_LOGRST_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYMUX_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYMUX_LOGRST_MASK 0x00000040                // CR_BAND1_PHYMUX_LOGRST[6]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYMUX_LOGRST_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYMISC_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYMISC_LOGRST_MASK 0x00000020                // CR_BAND1_PHYMISC_LOGRST[5]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_PHYMISC_LOGRST_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_OPOST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_OPOST_LOGRST_MASK 0x00000010                // CR_BAND1_OPOST_LOGRST[4]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_OPOST_LOGRST_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_FFT_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_FFT_LOGRST_MASK 0x00000008                // CR_BAND1_FFT_LOGRST[3]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_FFT_LOGRST_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXTD_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXTD_LOGRST_MASK 0x00000004                // CR_BAND1_RXTD_LOGRST[2]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXTD_LOGRST_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXFE_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXFE_LOGRST_MASK 0x00000002                // CR_BAND1_RXFE_LOGRST[1]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RXFE_LOGRST_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RFINTF_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RFINTF_LOGRST_MASK 0x00000001                // CR_BAND1_RFINTF_LOGRST[0]
#define WF_PHYRX_CTRL_CR_BAND1_RST_CTRL_CR_BAND1_RFINTF_LOGRST_SHFT 0

/* =====================================================================================

  ---B1_PHYRST_DISABLE_CTL (0x82000000 + 0x2024)---

    CR_BAND1_PHYRST_DISABLE_CTL[7..0] - (RW) [DE] BBP control CR
    CR_BAND1_PTA_SX_2WF[8]       - (RW) [DE] BBP control CR
    CR_BAND1_PTA_SX_2WF_MANU[9]  - (RW) [DE] BBP control CR
    RESERVED10[15..10]           - (RO) Reserved bits
    CR_BAND1_VAR_CKCTL[19..16]   - (RW) [DE] BBP control CR
    RESERVED20[27..20]           - (RO) Reserved bits
    CR_WF3_RFINTF_LOGRST[28]     - (RW) [DE] BBP control CR
    CR_WF2_RFINTF_LOGRST[29]     - (RW) [DE] BBP control CR
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_WF2_RFINTF_LOGRST_ADDR WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_WF2_RFINTF_LOGRST_MASK 0x20000000                // CR_WF2_RFINTF_LOGRST[29]
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_WF2_RFINTF_LOGRST_SHFT 29
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_WF3_RFINTF_LOGRST_ADDR WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_WF3_RFINTF_LOGRST_MASK 0x10000000                // CR_WF3_RFINTF_LOGRST[28]
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_WF3_RFINTF_LOGRST_SHFT 28
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_VAR_CKCTL_ADDR WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_VAR_CKCTL_MASK 0x000F0000                // CR_BAND1_VAR_CKCTL[19..16]
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_VAR_CKCTL_SHFT 16
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PTA_SX_2WF_MANU_ADDR WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PTA_SX_2WF_MANU_MASK 0x00000200                // CR_BAND1_PTA_SX_2WF_MANU[9]
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PTA_SX_2WF_MANU_SHFT 9
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PTA_SX_2WF_ADDR WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PTA_SX_2WF_MASK 0x00000100                // CR_BAND1_PTA_SX_2WF[8]
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PTA_SX_2WF_SHFT 8
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PHYRST_DISABLE_CTL_ADDR WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_ADDR
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PHYRST_DISABLE_CTL_MASK 0x000000FF                // CR_BAND1_PHYRST_DISABLE_CTL[7..0]
#define WF_PHYRX_CTRL_B1_PHYRST_DISABLE_CTL_CR_BAND1_PHYRST_DISABLE_CTL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_FRONT_RSVD1 (0x82000000 + 0x2030)---

    CR_BAND1_RDD_WAKEUP_IRQ_EN[0] - (RW) [DE] BBP control CR
    CR_BAND1_RDD_ERROR_IRQ_EN[1] - (RW) [DE] BBP control CR
    CR_BAND1_RX_ERR_WI_TRX[2]    - (RW) [DE] BBP control CR
    RESERVED3[11..3]             - (RO) Reserved bits
    CR_BAND1_OUT_FIFO_FREE_RUN[12] - (RW) [DE] BBP control CR
    CR_BAND1_OUT_FIFO_MODE_SEL[13] - (RW) [DE] BBP control CR
    RESERVED14[31..14]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_OUT_FIFO_MODE_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_OUT_FIFO_MODE_SEL_MASK 0x00002000                // CR_BAND1_OUT_FIFO_MODE_SEL[13]
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_OUT_FIFO_MODE_SEL_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_OUT_FIFO_FREE_RUN_ADDR WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_OUT_FIFO_FREE_RUN_MASK 0x00001000                // CR_BAND1_OUT_FIFO_FREE_RUN[12]
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_OUT_FIFO_FREE_RUN_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RX_ERR_WI_TRX_ADDR WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RX_ERR_WI_TRX_MASK 0x00000004                // CR_BAND1_RX_ERR_WI_TRX[2]
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RX_ERR_WI_TRX_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RDD_ERROR_IRQ_EN_ADDR WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RDD_ERROR_IRQ_EN_MASK 0x00000002                // CR_BAND1_RDD_ERROR_IRQ_EN[1]
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RDD_ERROR_IRQ_EN_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RDD_WAKEUP_IRQ_EN_ADDR WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RDD_WAKEUP_IRQ_EN_MASK 0x00000001                // CR_BAND1_RDD_WAKEUP_IRQ_EN[0]
#define WF_PHYRX_CTRL_CR_BAND1_FRONT_RSVD1_CR_BAND1_RDD_WAKEUP_IRQ_EN_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MON_FLAG_CTRL (0x82000000 + 0x220C)---

    CR_BAND1_MON_LSEL[7..0]      - (RW) [DE] BBP control CR
    CR_BAND1_MON_HSEL[15..8]     - (RW) [DE] BBP control CR
    CR_BAND1_MON_LMOD0[23..16]   - (RW) [DE] BBP control CR
    CR_BAND1_MON_HMOD0[31..24]   - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_HMOD0_ADDR WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_HMOD0_MASK 0xFF000000                // CR_BAND1_MON_HMOD0[31..24]
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_HMOD0_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_LMOD0_ADDR WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_LMOD0_MASK 0x00FF0000                // CR_BAND1_MON_LMOD0[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_LMOD0_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_HSEL_ADDR WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_HSEL_MASK 0x0000FF00                // CR_BAND1_MON_HSEL[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_HSEL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_LSEL_ADDR WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_LSEL_MASK 0x000000FF                // CR_BAND1_MON_LSEL[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_MON_FLAG_CTRL_CR_BAND1_MON_LSEL_SHFT 0

/* =====================================================================================

  ---RO_BAND1_MON_FLAG_STATUS0 (0x82000000 + 0x2210)---

    RO_BAND1_MON_FLAG_STATUS0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS0_RO_BAND1_MON_FLAG_STATUS0_ADDR WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS0_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS0_RO_BAND1_MON_FLAG_STATUS0_MASK 0xFFFFFFFF                // RO_BAND1_MON_FLAG_STATUS0[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS0_RO_BAND1_MON_FLAG_STATUS0_SHFT 0

/* =====================================================================================

  ---RO_BAND1_MON_FLAG_STATUS1 (0x82000000 + 0x2214)---

    RO_BAND1_MON_FLAG_STATUS1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS1_RO_BAND1_MON_FLAG_STATUS1_ADDR WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS1_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS1_RO_BAND1_MON_FLAG_STATUS1_MASK 0xFFFFFFFF                // RO_BAND1_MON_FLAG_STATUS1[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_MON_FLAG_STATUS1_RO_BAND1_MON_FLAG_STATUS1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT_RST_MASK (0x82000000 + 0x2218)---

    CR_BAND1_TRX_WDT_RST_MASK[31..0] - (RW) 1: Reset

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_RST_MASK_CR_BAND1_TRX_WDT_RST_MASK_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_RST_MASK_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_RST_MASK_CR_BAND1_TRX_WDT_RST_MASK_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT_RST_MASK[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_RST_MASK_CR_BAND1_TRX_WDT_RST_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND1_RST_TXFE_CTRL (0x82000000 + 0x221C)---

    CR_WF2_TXFE_RST_DLY_RISE[7..0] - (RW) [DE] BBP control CR
    CR_WF2_TXFE_RST_DLY_FALL[15..8] - (RW) [DE] BBP control CR
    CR_WF3_TXFE_RST_DLY_RISE[23..16] - (RW) [DE] BBP control CR
    CR_WF3_TXFE_RST_DLY_FALL[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF3_TXFE_RST_DLY_FALL_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF3_TXFE_RST_DLY_FALL_MASK 0xFF000000                // CR_WF3_TXFE_RST_DLY_FALL[31..24]
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF3_TXFE_RST_DLY_FALL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF3_TXFE_RST_DLY_RISE_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF3_TXFE_RST_DLY_RISE_MASK 0x00FF0000                // CR_WF3_TXFE_RST_DLY_RISE[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF3_TXFE_RST_DLY_RISE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF2_TXFE_RST_DLY_FALL_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF2_TXFE_RST_DLY_FALL_MASK 0x0000FF00                // CR_WF2_TXFE_RST_DLY_FALL[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF2_TXFE_RST_DLY_FALL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF2_TXFE_RST_DLY_RISE_ADDR WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF2_TXFE_RST_DLY_RISE_MASK 0x000000FF                // CR_WF2_TXFE_RST_DLY_RISE[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_RST_TXFE_CTRL_CR_WF2_TXFE_RST_DLY_RISE_SHFT 0

/* =====================================================================================

  ---RO_BAND1_MISC_IRQ_STA (0x82000000 + 0x2220)---

    RO_BAND1_IRQ_STA[31..0]      - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_MISC_IRQ_STA_RO_BAND1_IRQ_STA_ADDR WF_PHYRX_CTRL_RO_BAND1_MISC_IRQ_STA_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_MISC_IRQ_STA_RO_BAND1_IRQ_STA_MASK 0xFFFFFFFF                // RO_BAND1_IRQ_STA[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_MISC_IRQ_STA_RO_BAND1_IRQ_STA_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TXFD_TXTD_CTRL (0x82000000 + 0x2230)---

    CR_BAND1_DLY_FALL_TXTD[7..0] - (RW) [DE] BBP control CR
    CR_BAND1_DLY_RISE_TXTD[15..8] - (RW) [DE] BBP control CR
    CR_BAND1_DLY_FALL_TXFD[23..16] - (RW) [DE] BBP control CR
    CR_BAND1_DLY_RISE_TXFD[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_RISE_TXFD_ADDR WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_RISE_TXFD_MASK 0xFF000000                // CR_BAND1_DLY_RISE_TXFD[31..24]
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_RISE_TXFD_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_FALL_TXFD_ADDR WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_FALL_TXFD_MASK 0x00FF0000                // CR_BAND1_DLY_FALL_TXFD[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_FALL_TXFD_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_RISE_TXTD_ADDR WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_RISE_TXTD_MASK 0x0000FF00                // CR_BAND1_DLY_RISE_TXTD[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_RISE_TXTD_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_FALL_TXTD_ADDR WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_FALL_TXTD_MASK 0x000000FF                // CR_BAND1_DLY_FALL_TXTD[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_TXFD_TXTD_CTRL_CR_BAND1_DLY_FALL_TXTD_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MISC_CTRL (0x82000000 + 0x2248)---

    CR_BAND1_CLR_PHYCTRL_INT[0]  - (RW) [DE] BBP control CR
    CR_BAND1_CLR_WIFI_ERROR_TRIG[1] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD_WAKEUP_IRQ[2] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD_ERROR_IRQ[3] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_MUTX_TX_ERR_EVENT[4] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_MUTX_LQ_ERR_EVENT[5] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_TRX_WDT_TRIG[6] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_SPI_FAIL_IND[7] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_PFMU_IBF_TIMER_EXPIRE[8] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_PFMU_IBF_TIMER_RENEW[9] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD1_WAKEUP_IRQ[10] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD1_ERROR_IRQ[11] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD2_WAKEUP_IRQ[12] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD2_ERROR_IRQ[13] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD3_WAKEUP_IRQ[14] - (RW) [DE] BBP control CR
    CR_BAND1_CLR_RDD3_ERROR_IRQ[15] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_PHYCTRL_INT[16] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_WIFI_ERROR_TRIG[17] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD_WAKEUP_IRQ[18] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD_ERROR_IRQ[19] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_MUTX_TX_ERR_EVENT[20] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_MUTX_LQ_ERR_EVENT[21] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_TRX_WDT_TRIG[22] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_SPI_FAIL_IND[23] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_PFMU_IBF_TIMER_EXPIRE[24] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_PFMU_IBF_TIMER_RENEW[25] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD1_WAKEUP_IRQ[26] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD1_ERROR_IRQ[27] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD2_WAKEUP_IRQ[28] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD2_ERROR_IRQ[29] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD3_WAKEUP_IRQ[30] - (RW) [DE] BBP control CR
    CR_BAND1_ENA_RDD3_ERROR_IRQ[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD3_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD3_ERROR_IRQ_MASK 0x80000000                // CR_BAND1_ENA_RDD3_ERROR_IRQ[31]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD3_ERROR_IRQ_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD3_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD3_WAKEUP_IRQ_MASK 0x40000000                // CR_BAND1_ENA_RDD3_WAKEUP_IRQ[30]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD3_WAKEUP_IRQ_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD2_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD2_ERROR_IRQ_MASK 0x20000000                // CR_BAND1_ENA_RDD2_ERROR_IRQ[29]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD2_ERROR_IRQ_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD2_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD2_WAKEUP_IRQ_MASK 0x10000000                // CR_BAND1_ENA_RDD2_WAKEUP_IRQ[28]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD2_WAKEUP_IRQ_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD1_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD1_ERROR_IRQ_MASK 0x08000000                // CR_BAND1_ENA_RDD1_ERROR_IRQ[27]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD1_ERROR_IRQ_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD1_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD1_WAKEUP_IRQ_MASK 0x04000000                // CR_BAND1_ENA_RDD1_WAKEUP_IRQ[26]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD1_WAKEUP_IRQ_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PFMU_IBF_TIMER_RENEW_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PFMU_IBF_TIMER_RENEW_MASK 0x02000000                // CR_BAND1_ENA_PFMU_IBF_TIMER_RENEW[25]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PFMU_IBF_TIMER_RENEW_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PFMU_IBF_TIMER_EXPIRE_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PFMU_IBF_TIMER_EXPIRE_MASK 0x01000000                // CR_BAND1_ENA_PFMU_IBF_TIMER_EXPIRE[24]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PFMU_IBF_TIMER_EXPIRE_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_SPI_FAIL_IND_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_SPI_FAIL_IND_MASK 0x00800000                // CR_BAND1_ENA_SPI_FAIL_IND[23]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_SPI_FAIL_IND_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_TRX_WDT_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_TRX_WDT_TRIG_MASK 0x00400000                // CR_BAND1_ENA_TRX_WDT_TRIG[22]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_TRX_WDT_TRIG_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_MUTX_LQ_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_MUTX_LQ_ERR_EVENT_MASK 0x00200000                // CR_BAND1_ENA_MUTX_LQ_ERR_EVENT[21]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_MUTX_LQ_ERR_EVENT_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_MUTX_TX_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_MUTX_TX_ERR_EVENT_MASK 0x00100000                // CR_BAND1_ENA_MUTX_TX_ERR_EVENT[20]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_MUTX_TX_ERR_EVENT_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD_ERROR_IRQ_MASK 0x00080000                // CR_BAND1_ENA_RDD_ERROR_IRQ[19]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD_ERROR_IRQ_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD_WAKEUP_IRQ_MASK 0x00040000                // CR_BAND1_ENA_RDD_WAKEUP_IRQ[18]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_RDD_WAKEUP_IRQ_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_WIFI_ERROR_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_WIFI_ERROR_TRIG_MASK 0x00020000                // CR_BAND1_ENA_WIFI_ERROR_TRIG[17]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_WIFI_ERROR_TRIG_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PHYCTRL_INT_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PHYCTRL_INT_MASK 0x00010000                // CR_BAND1_ENA_PHYCTRL_INT[16]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_ENA_PHYCTRL_INT_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD3_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD3_ERROR_IRQ_MASK 0x00008000                // CR_BAND1_CLR_RDD3_ERROR_IRQ[15]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD3_ERROR_IRQ_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD3_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD3_WAKEUP_IRQ_MASK 0x00004000                // CR_BAND1_CLR_RDD3_WAKEUP_IRQ[14]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD3_WAKEUP_IRQ_SHFT 14
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD2_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD2_ERROR_IRQ_MASK 0x00002000                // CR_BAND1_CLR_RDD2_ERROR_IRQ[13]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD2_ERROR_IRQ_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD2_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD2_WAKEUP_IRQ_MASK 0x00001000                // CR_BAND1_CLR_RDD2_WAKEUP_IRQ[12]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD2_WAKEUP_IRQ_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD1_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD1_ERROR_IRQ_MASK 0x00000800                // CR_BAND1_CLR_RDD1_ERROR_IRQ[11]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD1_ERROR_IRQ_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD1_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD1_WAKEUP_IRQ_MASK 0x00000400                // CR_BAND1_CLR_RDD1_WAKEUP_IRQ[10]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD1_WAKEUP_IRQ_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PFMU_IBF_TIMER_RENEW_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PFMU_IBF_TIMER_RENEW_MASK 0x00000200                // CR_BAND1_CLR_PFMU_IBF_TIMER_RENEW[9]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PFMU_IBF_TIMER_RENEW_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PFMU_IBF_TIMER_EXPIRE_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PFMU_IBF_TIMER_EXPIRE_MASK 0x00000100                // CR_BAND1_CLR_PFMU_IBF_TIMER_EXPIRE[8]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PFMU_IBF_TIMER_EXPIRE_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_SPI_FAIL_IND_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_SPI_FAIL_IND_MASK 0x00000080                // CR_BAND1_CLR_SPI_FAIL_IND[7]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_SPI_FAIL_IND_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_TRX_WDT_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_TRX_WDT_TRIG_MASK 0x00000040                // CR_BAND1_CLR_TRX_WDT_TRIG[6]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_TRX_WDT_TRIG_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_MUTX_LQ_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_MUTX_LQ_ERR_EVENT_MASK 0x00000020                // CR_BAND1_CLR_MUTX_LQ_ERR_EVENT[5]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_MUTX_LQ_ERR_EVENT_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_MUTX_TX_ERR_EVENT_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_MUTX_TX_ERR_EVENT_MASK 0x00000010                // CR_BAND1_CLR_MUTX_TX_ERR_EVENT[4]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_MUTX_TX_ERR_EVENT_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD_ERROR_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD_ERROR_IRQ_MASK 0x00000008                // CR_BAND1_CLR_RDD_ERROR_IRQ[3]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD_ERROR_IRQ_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD_WAKEUP_IRQ_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD_WAKEUP_IRQ_MASK 0x00000004                // CR_BAND1_CLR_RDD_WAKEUP_IRQ[2]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_RDD_WAKEUP_IRQ_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_WIFI_ERROR_TRIG_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_WIFI_ERROR_TRIG_MASK 0x00000002                // CR_BAND1_CLR_WIFI_ERROR_TRIG[1]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_WIFI_ERROR_TRIG_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PHYCTRL_INT_ADDR WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PHYCTRL_INT_MASK 0x00000001                // CR_BAND1_CLR_PHYCTRL_INT[0]
#define WF_PHYRX_CTRL_CR_BAND1_MISC_CTRL_CR_BAND1_CLR_PHYCTRL_INT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_FFT_MANU_CTRL (0x82000000 + 0x2300)---

    CR_BAND1_FFT_MANU_CTRL[31..0] - (RW) [CSD] Band1 FFT manual mode for RXFDIQ calibration

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_FFT_MANU_CTRL_CR_BAND1_FFT_MANU_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_FFT_MANU_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FFT_MANU_CTRL_CR_BAND1_FFT_MANU_CTRL_MASK 0xFFFFFFFF                // CR_BAND1_FFT_MANU_CTRL[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_FFT_MANU_CTRL_CR_BAND1_FFT_MANU_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_FFT_BUFF_CTRL (0x82000000 + 0x2304)---

    RESERVED0[3..0]              - (RO) Reserved bits
    CR_BAND1_FFT_BUFF_RADDR[11..4] - (RW) [CSD] Band1 FFT buffer manual mode for RXFDIQ calibration
    CR_BAND1_FFT_BUFF_RA_UPD[12] - (RW) [CSD] Band1 FFT buffer manual mode for RXFDIQ calibration
    RESERVED13[14..13]           - (RO) Reserved bits
    CR_BAND1_FFT_BUFF_RD_RLS[15] - (RW) [CSD] Band1 FFT buffer manual mode for RXFDIQ calibration
    RO_BAND1_FFT_BUFF_RATRB[23..16] - (RO) [CSD] Band1 FFT buffer manual mode for RXFDIQ calibration
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_RO_BAND1_FFT_BUFF_RATRB_ADDR WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_RO_BAND1_FFT_BUFF_RATRB_MASK 0x00FF0000                // RO_BAND1_FFT_BUFF_RATRB[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_RO_BAND1_FFT_BUFF_RATRB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RD_RLS_ADDR WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RD_RLS_MASK 0x00008000                // CR_BAND1_FFT_BUFF_RD_RLS[15]
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RD_RLS_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RA_UPD_ADDR WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RA_UPD_MASK 0x00001000                // CR_BAND1_FFT_BUFF_RA_UPD[12]
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RA_UPD_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RADDR_ADDR WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RADDR_MASK 0x00000FF0                // CR_BAND1_FFT_BUFF_RADDR[11..4]
#define WF_PHYRX_CTRL_CR_BAND1_FFT_BUFF_CTRL_CR_BAND1_FFT_BUFF_RADDR_SHFT 4

/* =====================================================================================

  ---RO_BAND1_FFT_BUFF_READ (0x82000000 + 0x2308)---

    RO_BAND1_FFT_BUFF_RDATA[23..0] - (RO) [CSD] Band1 FFT buffer manual mode for RXFDIQ calibration
    RESERVED24[30..24]           - (RO) Reserved bits
    CR_BAND1_FFT_BUFF_RD_UPD[31] - (RS) [CSD] Band1 FFT buffer manual mode for RXFDIQ calibration

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_CR_BAND1_FFT_BUFF_RD_UPD_ADDR WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_CR_BAND1_FFT_BUFF_RD_UPD_MASK 0x80000000                // CR_BAND1_FFT_BUFF_RD_UPD[31]
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_CR_BAND1_FFT_BUFF_RD_UPD_SHFT 31
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_RO_BAND1_FFT_BUFF_RDATA_ADDR WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_RO_BAND1_FFT_BUFF_RDATA_MASK 0x00FFFFFF                // RO_BAND1_FFT_BUFF_RDATA[23..0]
#define WF_PHYRX_CTRL_RO_BAND1_FFT_BUFF_READ_RO_BAND1_FFT_BUFF_RDATA_SHFT 0

/* =====================================================================================

  ---RO_BAND1_FFT_CSD_DBG (0x82000000 + 0x230C)---

    RO_BAND1_FFT_CSD_DBG[12..0]  - (RO) [CSD] Band1 FFT Debug flag
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_FFT_CSD_DBG_RO_BAND1_FFT_CSD_DBG_ADDR WF_PHYRX_CTRL_RO_BAND1_FFT_CSD_DBG_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_FFT_CSD_DBG_RO_BAND1_FFT_CSD_DBG_MASK 0x00001FFF                // RO_BAND1_FFT_CSD_DBG[12..0]
#define WF_PHYRX_CTRL_RO_BAND1_FFT_CSD_DBG_RO_BAND1_FFT_CSD_DBG_SHFT 0

/* =====================================================================================

  ---RO_BAND1_STAT_CORE (0x82000000 + 0x2310)---

    RO_BAND1_STAT_CORE[31..0]    - (RO) [DE] Band1 FFT CORE status monitor

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_STAT_CORE_RO_BAND1_STAT_CORE_ADDR WF_PHYRX_CTRL_RO_BAND1_STAT_CORE_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_STAT_CORE_RO_BAND1_STAT_CORE_MASK 0xFFFFFFFF                // RO_BAND1_STAT_CORE[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_STAT_CORE_RO_BAND1_STAT_CORE_SHFT 0

/* =====================================================================================

  ---RO_BAND1_STAT_REQARB (0x82000000 + 0x2314)---

    RO_BAND1_STAT_REQARB[31..0]  - (RO) [DE] Band1 FFT REQARB status monitor

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_STAT_REQARB_RO_BAND1_STAT_REQARB_ADDR WF_PHYRX_CTRL_RO_BAND1_STAT_REQARB_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_STAT_REQARB_RO_BAND1_STAT_REQARB_MASK 0xFFFFFFFF                // RO_BAND1_STAT_REQARB[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_STAT_REQARB_RO_BAND1_STAT_REQARB_SHFT 0

/* =====================================================================================

  ---RO_BAND1_DBGSGD_LYR0_TRIG (0x82000000 + 0x2428)---

    RO_BAND1_SGD_LYR0_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR0_TRIG_RO_BAND1_SGD_LYR0_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR0_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR0_TRIG_RO_BAND1_SGD_LYR0_TRIG_MASK 0xFFFFFFFF                // RO_BAND1_SGD_LYR0_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR0_TRIG_RO_BAND1_SGD_LYR0_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND1_DBGSGD_LYR1_TRIG (0x82000000 + 0x242C)---

    RO_BAND1_SGD_LYR1_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR1_TRIG_RO_BAND1_SGD_LYR1_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR1_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR1_TRIG_RO_BAND1_SGD_LYR1_TRIG_MASK 0xFFFFFFFF                // RO_BAND1_SGD_LYR1_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR1_TRIG_RO_BAND1_SGD_LYR1_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND1_DBGSGD_LYR2_TRIG (0x82000000 + 0x2430)---

    RO_BAND1_SGD_LYR2_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR2_TRIG_RO_BAND1_SGD_LYR2_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR2_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR2_TRIG_RO_BAND1_SGD_LYR2_TRIG_MASK 0xFFFFFFFF                // RO_BAND1_SGD_LYR2_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR2_TRIG_RO_BAND1_SGD_LYR2_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND1_DBGSGD_LYR3_TRIG (0x82000000 + 0x2434)---

    RO_BAND1_SGD_LYR3_TRIG[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR3_TRIG_RO_BAND1_SGD_LYR3_TRIG_ADDR WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR3_TRIG_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR3_TRIG_RO_BAND1_SGD_LYR3_TRIG_MASK 0xFFFFFFFF                // RO_BAND1_SGD_LYR3_TRIG[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_LYR3_TRIG_RO_BAND1_SGD_LYR3_TRIG_SHFT 0

/* =====================================================================================

  ---RO_BAND1_DBGSGD_TRGFSM (0x82000000 + 0x2438)---

    RO_BAND1_SGD_TRGFSM[31..0]   - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_TRGFSM_RO_BAND1_SGD_TRGFSM_ADDR WF_PHYRX_CTRL_RO_BAND1_DBGSGD_TRGFSM_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_TRGFSM_RO_BAND1_SGD_TRGFSM_MASK 0xFFFFFFFF                // RO_BAND1_SGD_TRGFSM[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_DBGSGD_TRGFSM_RO_BAND1_SGD_TRGFSM_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT1_MASK3 (0x82000000 + 0x2490)---

    CR_BAND1_TRX_WDT1_MASK3[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK3_CR_BAND1_TRX_WDT1_MASK3_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK3_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK3_CR_BAND1_TRX_WDT1_MASK3_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT1_MASK3[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK3_CR_BAND1_TRX_WDT1_MASK3_SHFT 0

/* =====================================================================================

  ---RO_BAND1_TRX_WDT1_STAT (0x82000000 + 0x2494)---

    RO_BAND1_TRX_WDT1_STAT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT1_STAT_RO_BAND1_TRX_WDT1_STAT_ADDR WF_PHYRX_CTRL_RO_BAND1_TRX_WDT1_STAT_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT1_STAT_RO_BAND1_TRX_WDT1_STAT_MASK 0xFFFFFFFF                // RO_BAND1_TRX_WDT1_STAT[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT1_STAT_RO_BAND1_TRX_WDT1_STAT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT_CTRL (0x82000000 + 0x2500)---

    CR_BAND1_TRX_WDT_COUNT[29..0] - (RW) [DE] BBP control CR
    CR_BAND1_TRX_WDT_COND[30]    - (RW) [DE] BBP control CR
    CR_BAND1_TRX_WDT_ENA[31]     - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_ENA_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_ENA_MASK 0x80000000                // CR_BAND1_TRX_WDT_ENA[31]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_ENA_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_COND_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_COND_MASK 0x40000000                // CR_BAND1_TRX_WDT_COND[30]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_COND_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_COUNT_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_COUNT_MASK 0x3FFFFFFF                // CR_BAND1_TRX_WDT_COUNT[29..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_CTRL_CR_BAND1_TRX_WDT_COUNT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT_MASK0 (0x82000000 + 0x2504)---

    CR_BAND1_TRX_WDT_MASK0[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK0_CR_BAND1_TRX_WDT_MASK0_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK0_CR_BAND1_TRX_WDT_MASK0_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT_MASK0[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK0_CR_BAND1_TRX_WDT_MASK0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT_MASK1 (0x82000000 + 0x2508)---

    CR_BAND1_TRX_WDT_MASK1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK1_CR_BAND1_TRX_WDT_MASK1_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK1_CR_BAND1_TRX_WDT_MASK1_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT_MASK1[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK1_CR_BAND1_TRX_WDT_MASK1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT_MASK2 (0x82000000 + 0x250C)---

    CR_BAND1_TRX_WDT_MASK2[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK2_CR_BAND1_TRX_WDT_MASK2_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK2_CR_BAND1_TRX_WDT_MASK2_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT_MASK2[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK2_CR_BAND1_TRX_WDT_MASK2_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT_MASK3 (0x82000000 + 0x2510)---

    CR_BAND1_TRX_WDT_MASK3[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK3_CR_BAND1_TRX_WDT_MASK3_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK3_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK3_CR_BAND1_TRX_WDT_MASK3_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT_MASK3[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT_MASK3_CR_BAND1_TRX_WDT_MASK3_SHFT 0

/* =====================================================================================

  ---RO_BAND1_TRX_WDT_STAT (0x82000000 + 0x2514)---

    RO_BAND1_TRX_WDT_STAT[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT_STAT_RO_BAND1_TRX_WDT_STAT_ADDR WF_PHYRX_CTRL_RO_BAND1_TRX_WDT_STAT_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT_STAT_RO_BAND1_TRX_WDT_STAT_MASK 0xFFFFFFFF                // RO_BAND1_TRX_WDT_STAT[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TRX_WDT_STAT_RO_BAND1_TRX_WDT_STAT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT1_CTRL (0x82000000 + 0x2580)---

    CR_BAND1_TRX_WDT1_COUNT[29..0] - (RW) [DE] BBP control CR
    CR_BAND1_TRX_WDT1_COND[30]   - (RW) [DE] BBP control CR
    CR_BAND1_TRX_WDT1_ENA[31]    - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_ENA_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_ENA_MASK 0x80000000                // CR_BAND1_TRX_WDT1_ENA[31]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_ENA_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_COND_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_COND_MASK 0x40000000                // CR_BAND1_TRX_WDT1_COND[30]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_COND_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_COUNT_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_COUNT_MASK 0x3FFFFFFF                // CR_BAND1_TRX_WDT1_COUNT[29..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_CTRL_CR_BAND1_TRX_WDT1_COUNT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT1_MASK0 (0x82000000 + 0x2584)---

    CR_BAND1_TRX_WDT1_MASK0[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK0_CR_BAND1_TRX_WDT1_MASK0_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK0_CR_BAND1_TRX_WDT1_MASK0_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT1_MASK0[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK0_CR_BAND1_TRX_WDT1_MASK0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT1_MASK1 (0x82000000 + 0x2588)---

    CR_BAND1_TRX_WDT1_MASK1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK1_CR_BAND1_TRX_WDT1_MASK1_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK1_CR_BAND1_TRX_WDT1_MASK1_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT1_MASK1[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK1_CR_BAND1_TRX_WDT1_MASK1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TRX_WDT1_MASK2 (0x82000000 + 0x258C)---

    CR_BAND1_TRX_WDT1_MASK2[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK2_CR_BAND1_TRX_WDT1_MASK2_ADDR WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK2_CR_BAND1_TRX_WDT1_MASK2_MASK 0xFFFFFFFF                // CR_BAND1_TRX_WDT1_MASK2[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_TRX_WDT1_MASK2_CR_BAND1_TRX_WDT1_MASK2_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_0 (0x82000000 + 0x2C00)---

    CR_RDD1_HPF_ALPHA_BW20_0[2..0] - (RW) alpha value for BW20
    CR_RDD1_HPF_ALPHA_BW20_1[5..3] - (RW) alpha value for BW20 (state = 1)
    CR_RDD1_HPF_ALPHA_BW40_0[8..6] - (RW) alpha value for BW40
    CR_RDD1_HPF_ALPHA_BW40_1[11..9] - (RW) alpha value for BW40 (state = 1)
    CR_RDD1_HPF_STATE_CNT_TH[14..12] - (RW) HPF state counter threshold for state = 1
    CR_RDD1_ACI_IGNORE_DC[15]    - (RW) Ignore DC when ACI
    CR_RDD1_HPF_ALPHA_BW80_0[18..16] - (RW) alpha value for BW80
    CR_RDD1_HPF_ALPHA_BW80_1[21..19] - (RW) alpha value for BW80 (state = 1)
    CR_RDD1_HPF_ALPHA_BW160_0[24..22] - (RW) alpha value for BW160
    CR_RDD1_HPF_ALPHA_BW160_1[27..25] - (RW) alpha value for BW160 (state = 1)
    CR_RDD1_GSWITCH_SETTLE_PRD[30..28] - (RW) agc gain switch settling period
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_GSWITCH_SETTLE_PRD_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_GSWITCH_SETTLE_PRD_MASK 0x70000000                // CR_RDD1_GSWITCH_SETTLE_PRD[30..28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_GSWITCH_SETTLE_PRD_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW160_1_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW160_1_MASK 0x0E000000                // CR_RDD1_HPF_ALPHA_BW160_1[27..25]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW160_1_SHFT 25
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW160_0_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW160_0_MASK 0x01C00000                // CR_RDD1_HPF_ALPHA_BW160_0[24..22]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW160_0_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW80_1_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW80_1_MASK 0x00380000                // CR_RDD1_HPF_ALPHA_BW80_1[21..19]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW80_1_SHFT 19
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW80_0_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW80_0_MASK 0x00070000                // CR_RDD1_HPF_ALPHA_BW80_0[18..16]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW80_0_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_ACI_IGNORE_DC_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_ACI_IGNORE_DC_MASK 0x00008000                // CR_RDD1_ACI_IGNORE_DC[15]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_ACI_IGNORE_DC_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_STATE_CNT_TH_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_STATE_CNT_TH_MASK 0x00007000                // CR_RDD1_HPF_STATE_CNT_TH[14..12]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_STATE_CNT_TH_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW40_1_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW40_1_MASK 0x00000E00                // CR_RDD1_HPF_ALPHA_BW40_1[11..9]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW40_1_SHFT 9
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW40_0_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW40_0_MASK 0x000001C0                // CR_RDD1_HPF_ALPHA_BW40_0[8..6]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW40_0_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW20_1_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW20_1_MASK 0x00000038                // CR_RDD1_HPF_ALPHA_BW20_1[5..3]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW20_1_SHFT 3
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW20_0_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW20_0_MASK 0x00000007                // CR_RDD1_HPF_ALPHA_BW20_0[2..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_0_CR_RDD1_HPF_ALPHA_BW20_0_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_1 (0x82000000 + 0x2C04)---

    CR_RDD1_DELTA_RSSI_AACI_TH[4..0] - (RW) delta rssi thrshold for AACI
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD1_DELTA_RSSI_ACI_TH[12..8] - (RW) delta rssi thrshold for ACI
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_RDD1_MIN_VALID_RSSI_WB_DBV[22..16] - (RW) min RSSI ib value for aci detection
    RESERVED23[23]               - (RO) Reserved bits
    CR_RDD1_MAX_VALID_RSSI_IB_DBV[30..24] - (RW) max RSSI ib value for aci detection
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_MAX_VALID_RSSI_IB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_MAX_VALID_RSSI_IB_DBV_MASK 0x7F000000                // CR_RDD1_MAX_VALID_RSSI_IB_DBV[30..24]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_MAX_VALID_RSSI_IB_DBV_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_MIN_VALID_RSSI_WB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_MIN_VALID_RSSI_WB_DBV_MASK 0x007F0000                // CR_RDD1_MIN_VALID_RSSI_WB_DBV[22..16]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_MIN_VALID_RSSI_WB_DBV_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_DELTA_RSSI_ACI_TH_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_DELTA_RSSI_ACI_TH_MASK 0x00001F00                // CR_RDD1_DELTA_RSSI_ACI_TH[12..8]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_DELTA_RSSI_ACI_TH_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_DELTA_RSSI_AACI_TH_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_DELTA_RSSI_AACI_TH_MASK 0x0000001F                // CR_RDD1_DELTA_RSSI_AACI_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_1_CR_RDD1_DELTA_RSSI_AACI_TH_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_2 (0x82000000 + 0x2C08)---

    CR_RDD1_DELTA_RSSI_0_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_RDD1_DELTA_RSSI_1_TH_ACI[11..6] - (RW) delta rssi threshold when aci_det =1
    CR_RDD1_AMSC_FAIL_RATIO_ACI[15..12] - (RW) ratio of amplitude stability check when aci_det =1
    CR_RDD1_DELTA_RSSI_0_TH_SEN[21..16] - (RW) delta rssi threshold when aci_det =0
    CR_RDD1_DELTA_RSSI_1_TH_SEN[27..22] - (RW) delta rssi threshold when aci_det =0
    CR_RDD1_AMSC_FAIL_RATIO_SEN[31..28] - (RW) ratio of amplitude stability check when aci_det =0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_AMSC_FAIL_RATIO_SEN_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_AMSC_FAIL_RATIO_SEN_MASK 0xF0000000                // CR_RDD1_AMSC_FAIL_RATIO_SEN[31..28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_AMSC_FAIL_RATIO_SEN_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_1_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_1_TH_SEN_MASK 0x0FC00000                // CR_RDD1_DELTA_RSSI_1_TH_SEN[27..22]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_1_TH_SEN_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_0_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_0_TH_SEN_MASK 0x003F0000                // CR_RDD1_DELTA_RSSI_0_TH_SEN[21..16]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_0_TH_SEN_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_AMSC_FAIL_RATIO_ACI_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_AMSC_FAIL_RATIO_ACI_MASK 0x0000F000                // CR_RDD1_AMSC_FAIL_RATIO_ACI[15..12]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_AMSC_FAIL_RATIO_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_1_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_1_TH_ACI_MASK 0x00000FC0                // CR_RDD1_DELTA_RSSI_1_TH_ACI[11..6]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_1_TH_ACI_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_0_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_0_TH_ACI_MASK 0x0000003F                // CR_RDD1_DELTA_RSSI_0_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_2_CR_RDD1_DELTA_RSSI_0_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_3 (0x82000000 + 0x2C0C)---

    CR_RDD1_DELTA_RSSI_2_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_RDD1_DELTA_RSSI_2_TH_SEN[11..6] - (RW) delta rssi threshold when aci_det =0
    CR_RDD1_NO_RISE_EDGE_FIX_GAIN_ENB[12] - (RW) no edge detection when agc fix gain
    CR_RDD1_FIRST_RISE_EDGE_ENB[13] - (RW) enable first rise edge as pulse
    RESERVED14[14]               - (RO) Reserved bits
    CR_RDD1_MAX_PULSE_WIDTH[23..15] - (RW) maximum pulse width
    CR_RDD1_MIN_RSSI_DBM[31..24] - (RW) mininum rssi_dbm value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_MIN_RSSI_DBM_ADDR  WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_MIN_RSSI_DBM_MASK  0xFF000000                // CR_RDD1_MIN_RSSI_DBM[31..24]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_MIN_RSSI_DBM_SHFT  24
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_MAX_PULSE_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_MAX_PULSE_WIDTH_MASK 0x00FF8000                // CR_RDD1_MAX_PULSE_WIDTH[23..15]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_MAX_PULSE_WIDTH_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_FIRST_RISE_EDGE_ENB_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_FIRST_RISE_EDGE_ENB_MASK 0x00002000                // CR_RDD1_FIRST_RISE_EDGE_ENB[13]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_FIRST_RISE_EDGE_ENB_SHFT 13
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_NO_RISE_EDGE_FIX_GAIN_ENB_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_NO_RISE_EDGE_FIX_GAIN_ENB_MASK 0x00001000                // CR_RDD1_NO_RISE_EDGE_FIX_GAIN_ENB[12]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_NO_RISE_EDGE_FIX_GAIN_ENB_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_DELTA_RSSI_2_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_DELTA_RSSI_2_TH_SEN_MASK 0x00000FC0                // CR_RDD1_DELTA_RSSI_2_TH_SEN[11..6]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_DELTA_RSSI_2_TH_SEN_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_DELTA_RSSI_2_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_DELTA_RSSI_2_TH_ACI_MASK 0x0000003F                // CR_RDD1_DELTA_RSSI_2_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_3_CR_RDD1_DELTA_RSSI_2_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_4 (0x82000000 + 0x2C10)---

    CR_RDD1_SC_DROP_RATIO[3..0]  - (RW) stability drop ration
    CR_RDD1_SC_CHECK_CNT_DROP[9..4] - (RW) stability check counter value for drop
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_RDD1_SC_PASS_RATIO[15..12] - (RW) stability pass ratio
    CR_RDD1_SC_CHECK_CNT_PASS[21..16] - (RW) stability check counter value for pass
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_RDD1_MIN_PULSE_POWER[31..24] - (RW) mininum pulse power

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_MIN_PULSE_POWER_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_MIN_PULSE_POWER_MASK 0xFF000000                // CR_RDD1_MIN_PULSE_POWER[31..24]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_MIN_PULSE_POWER_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_CHECK_CNT_PASS_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_CHECK_CNT_PASS_MASK 0x003F0000                // CR_RDD1_SC_CHECK_CNT_PASS[21..16]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_CHECK_CNT_PASS_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_PASS_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_PASS_RATIO_MASK 0x0000F000                // CR_RDD1_SC_PASS_RATIO[15..12]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_PASS_RATIO_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_CHECK_CNT_DROP_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_CHECK_CNT_DROP_MASK 0x000003F0                // CR_RDD1_SC_CHECK_CNT_DROP[9..4]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_CHECK_CNT_DROP_SHFT 4
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_DROP_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_DROP_RATIO_MASK 0x0000000F                // CR_RDD1_SC_DROP_RATIO[3..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_4_CR_RDD1_SC_DROP_RATIO_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_5 (0x82000000 + 0x2C14)---

    CR_RDD1_WAKE_UP_PERIOD[7..0] - (RW) send wake up IRQ after this value * 0.8192 ms
    CR_RDD1_WAKE_UP_PULSE_NUM[12..8] - (RW) send wake up IRQ when pulse number exceed this value
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_RDD1_NO_DET_PULSE_PERIOD[20..16] - (RW) send SW reset if no det_pulse during this value * 0.84 sec
    RESERVED21[21]               - (RO) Reserved bits
    CR_RDD1_ERROR_IRQ_EN[22]     - (RW) Enable interrupt (IRQ) when RDD wake up
    CR_RDD1_WAKEUP_IRQ_EN[23]    - (RW) Enable interrupt (IRQ) when RDD error
    CR_RDD1_PULSE_BUF_SEL[27..24] - (RW) select read out pulse number
    CR_RDD1_PULSE_BUF_CLR[28]    - (RW) clear pulse buffer and reset to 0
    RESERVED29[29]               - (RO) Reserved bits
    CR_RDD1_TEST_DET_PULSE[30]   - (RW) Manually generate pulse rise edge
    CR_RDD1_TEST_PULSE_EN[31]    - (RW) Send 32'haaaa_bbbb & 32'hcccc_dddd to AHB wrapper

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_TEST_PULSE_EN_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_TEST_PULSE_EN_MASK 0x80000000                // CR_RDD1_TEST_PULSE_EN[31]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_TEST_PULSE_EN_SHFT 31
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_TEST_DET_PULSE_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_TEST_DET_PULSE_MASK 0x40000000                // CR_RDD1_TEST_DET_PULSE[30]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_TEST_DET_PULSE_SHFT 30
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_PULSE_BUF_CLR_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_PULSE_BUF_CLR_MASK 0x10000000                // CR_RDD1_PULSE_BUF_CLR[28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_PULSE_BUF_CLR_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_PULSE_BUF_SEL_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_PULSE_BUF_SEL_MASK 0x0F000000                // CR_RDD1_PULSE_BUF_SEL[27..24]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_PULSE_BUF_SEL_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKEUP_IRQ_EN_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKEUP_IRQ_EN_MASK 0x00800000                // CR_RDD1_WAKEUP_IRQ_EN[23]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKEUP_IRQ_EN_SHFT 23
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_ERROR_IRQ_EN_ADDR  WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_ERROR_IRQ_EN_MASK  0x00400000                // CR_RDD1_ERROR_IRQ_EN[22]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_ERROR_IRQ_EN_SHFT  22
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_NO_DET_PULSE_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_NO_DET_PULSE_PERIOD_MASK 0x001F0000                // CR_RDD1_NO_DET_PULSE_PERIOD[20..16]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_NO_DET_PULSE_PERIOD_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKE_UP_PULSE_NUM_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKE_UP_PULSE_NUM_MASK 0x00001F00                // CR_RDD1_WAKE_UP_PULSE_NUM[12..8]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKE_UP_PULSE_NUM_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKE_UP_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKE_UP_PERIOD_MASK 0x000000FF                // CR_RDD1_WAKE_UP_PERIOD[7..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_5_CR_RDD1_WAKE_UP_PERIOD_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_6 (0x82000000 + 0x2C18)---

    RO_RDD1_PULSE_BUF_NUM[4..0]  - (RO) Number of pulses stored in buffer
    RESERVED5[7..5]              - (RO) Reserved bits
    RO_RDD1_WAKEUP_IRQ[8]        - (RO) RDD wake up interrupt
    RO_RDD1_ERROR_IRQ[9]         - (RO) RDD error interrupt
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_ERROR_IRQ_ADDR     WF_PHYRX_CTRL_CR_RDD1_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_ERROR_IRQ_MASK     0x00000200                // RO_RDD1_ERROR_IRQ[9]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_ERROR_IRQ_SHFT     9
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_WAKEUP_IRQ_ADDR    WF_PHYRX_CTRL_CR_RDD1_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_WAKEUP_IRQ_MASK    0x00000100                // RO_RDD1_WAKEUP_IRQ[8]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_WAKEUP_IRQ_SHFT    8
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_PULSE_BUF_NUM_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_PULSE_BUF_NUM_MASK 0x0000001F                // RO_RDD1_PULSE_BUF_NUM[4..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_6_RO_RDD1_PULSE_BUF_NUM_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_7 (0x82000000 + 0x2C1C)---

    RO_RDD1_PULSE_BUF_MSB[31..0] - (RO) Read out pulse data for FPGA debug (MSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_7_RO_RDD1_PULSE_BUF_MSB_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_7_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_7_RO_RDD1_PULSE_BUF_MSB_MASK 0xFFFFFFFF                // RO_RDD1_PULSE_BUF_MSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_7_RO_RDD1_PULSE_BUF_MSB_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_8 (0x82000000 + 0x2C20)---

    RO_RDD1_PULSE_BUF_LSB[31..0] - (RO) Read out pulse data for FPGA debug (LSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_8_RO_RDD1_PULSE_BUF_LSB_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_8_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_8_RO_RDD1_PULSE_BUF_LSB_MASK 0xFFFFFFFF                // RO_RDD1_PULSE_BUF_LSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_8_RO_RDD1_PULSE_BUF_LSB_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_12 (0x82000000 + 0x2C30)---

    CR_RDD1_MDRDY_START[6..0]    - (RW) RDD MDRDY start time
    CR_RDD1_MDRDY_END[13..7]     - (RW) RDD MDRDY end time
    CR_RDD1_MDRDY_SEL[14]        - (RW) MDRDY select, 0: MDRDY raising, 1: MDRDY trigger
    RESERVED15[26..15]           - (RO) Reserved bits
    CR_RDD1_CCA_SEL[28..27]      - (RW) [DE] BBP control CR
    CR_RDD1_BAND_SEL[29]         - (RW) [DE] BBP control CR
    CR_RDD1_ANT_SEL[31..30]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_ANT_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_ANT_SEL_MASK      0xC0000000                // CR_RDD1_ANT_SEL[31..30]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_ANT_SEL_SHFT      30
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_BAND_SEL_ADDR     WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_BAND_SEL_MASK     0x20000000                // CR_RDD1_BAND_SEL[29]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_BAND_SEL_SHFT     29
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_CCA_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_CCA_SEL_MASK      0x18000000                // CR_RDD1_CCA_SEL[28..27]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_CCA_SEL_SHFT      27
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_SEL_ADDR    WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_SEL_MASK    0x00004000                // CR_RDD1_MDRDY_SEL[14]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_SEL_SHFT    14
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_END_ADDR    WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_END_MASK    0x00003F80                // CR_RDD1_MDRDY_END[13..7]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_END_SHFT    7
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_START_ADDR  WF_PHYRX_CTRL_CR_RDD1_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_START_MASK  0x0000007F                // CR_RDD1_MDRDY_START[6..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_12_CR_RDD1_MDRDY_START_SHFT  0

/* =====================================================================================

  ---CR_RDD1_TOP_13 (0x82000000 + 0x2C34)---

    CR_RDD1_DC_RATIO_TH[4..0]    - (RW) dc pulse cnt ratio
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD1_MIN_RSSI_0_DBV_FOR_ED[14..8] - (RW) DBV for ED
    RESERVED15[20..15]           - (RO) Reserved bits
    CR_RDD1_ACI_EXIST_RATIO[25..21] - (RW) cr ACI exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD1_DISA_2BST[28]        - (RW) 1: Disable only one 2nd subband exist
                                     it means we can hold 3 subband as high
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_DISA_2BST_ADDR    WF_PHYRX_CTRL_CR_RDD1_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_DISA_2BST_MASK    0x10000000                // CR_RDD1_DISA_2BST[28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_DISA_2BST_SHFT    28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_ACI_EXIST_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_ACI_EXIST_RATIO_MASK 0x03E00000                // CR_RDD1_ACI_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_ACI_EXIST_RATIO_SHFT 21
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_MIN_RSSI_0_DBV_FOR_ED_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_MIN_RSSI_0_DBV_FOR_ED_MASK 0x00007F00                // CR_RDD1_MIN_RSSI_0_DBV_FOR_ED[14..8]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_MIN_RSSI_0_DBV_FOR_ED_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_DC_RATIO_TH_ADDR  WF_PHYRX_CTRL_CR_RDD1_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_DC_RATIO_TH_MASK  0x0000001F                // CR_RDD1_DC_RATIO_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_13_CR_RDD1_DC_RATIO_TH_SHFT  0

/* =====================================================================================

  ---CR_RDD1_TOP_14 (0x82000000 + 0x2C38)---

    CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0] - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12] - (RW) min cnt of ACI
    CR_RDD1_DC_EXIST_RATIO[25..21] - (RW) cr dc exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD1_RSSI_MAX_2ND_DIFF[31..28] - (RW) subband RSSI comparison,
                                     max subband and 2nd subband threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_RSSI_MAX_2ND_DIFF_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_RSSI_MAX_2ND_DIFF_MASK 0xF0000000                // CR_RDD1_RSSI_MAX_2ND_DIFF[31..28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_RSSI_MAX_2ND_DIFF_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_DC_EXIST_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_DC_EXIST_RATIO_MASK 0x03E00000                // CR_RDD1_DC_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_DC_EXIST_RATIO_SHFT 21
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_MASK 0x001FF000                // CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_MASK 0x000001FF                // CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_14_CR_RDD1_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_15 (0x82000000 + 0x2C3C)---

    CR_RDD1_MIN_LP_WIDTH[8..0]   - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_RDD1_MAX_PP_WIDTH[20..12] - (RW) min cnt of ACI
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_RDD1_ACI_CNT_AACI[27..24] - (RW) aaci initial value
    CR_RDD1_ACI_CNT_MAX[31..28]  - (RW) aci maxinum value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_ACI_CNT_MAX_ADDR  WF_PHYRX_CTRL_CR_RDD1_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_ACI_CNT_MAX_MASK  0xF0000000                // CR_RDD1_ACI_CNT_MAX[31..28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_ACI_CNT_MAX_SHFT  28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_ACI_CNT_AACI_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_ACI_CNT_AACI_MASK 0x0F000000                // CR_RDD1_ACI_CNT_AACI[27..24]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_ACI_CNT_AACI_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_MAX_PP_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_MAX_PP_WIDTH_MASK 0x001FF000                // CR_RDD1_MAX_PP_WIDTH[20..12]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_MAX_PP_WIDTH_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_MIN_LP_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_MIN_LP_WIDTH_MASK 0x000001FF                // CR_RDD1_MIN_LP_WIDTH[8..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_15_CR_RDD1_MIN_LP_WIDTH_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_16 (0x82000000 + 0x2C40)---

    CR_RDD1_ACI_CHECK_PRD[4..0]  - (RW) accumulation period times of RSSI update
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD1_CNT_ACI_DET_DROP[12..8] - (RW) threshold for detction of ACI times per 4us
    RESERVED13[19..13]           - (RO) Reserved bits
    CR_RDD1_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20] - (RW) count for aci min pulse check
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_MAX_PULSE_WIDTH_DO_ACI_CHECK_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_MAX_PULSE_WIDTH_DO_ACI_CHECK_MASK 0x1FF00000                // CR_RDD1_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_MAX_PULSE_WIDTH_DO_ACI_CHECK_SHFT 20
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_CNT_ACI_DET_DROP_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_CNT_ACI_DET_DROP_MASK 0x00001F00                // CR_RDD1_CNT_ACI_DET_DROP[12..8]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_CNT_ACI_DET_DROP_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_ACI_CHECK_PRD_ADDR WF_PHYRX_CTRL_CR_RDD1_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_ACI_CHECK_PRD_MASK 0x0000001F                // CR_RDD1_ACI_CHECK_PRD[4..0]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_16_CR_RDD1_ACI_CHECK_PRD_SHFT 0

/* =====================================================================================

  ---CR_RDD1_TOP_17 (0x82000000 + 0x2C44)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_RDD1_ACI_CNT_L[27..24]    - (RW) aci_cnt threshold
    CR_RDD1_ACI_CNT_H[31..28]    - (RW) aci_cnt threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_CR_RDD1_ACI_CNT_H_ADDR    WF_PHYRX_CTRL_CR_RDD1_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_CR_RDD1_ACI_CNT_H_MASK    0xF0000000                // CR_RDD1_ACI_CNT_H[31..28]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_CR_RDD1_ACI_CNT_H_SHFT    28
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_CR_RDD1_ACI_CNT_L_ADDR    WF_PHYRX_CTRL_CR_RDD1_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_CR_RDD1_ACI_CNT_L_MASK    0x0F000000                // CR_RDD1_ACI_CNT_L[27..24]
#define WF_PHYRX_CTRL_CR_RDD1_TOP_17_CR_RDD1_ACI_CNT_L_SHFT    24

/* =====================================================================================

  ---CR_RDD2_TOP_0 (0x82000000 + 0x2C50)---

    CR_RDD2_HPF_ALPHA_BW20_0[2..0] - (RW) alpha value for BW20
    CR_RDD2_HPF_ALPHA_BW20_1[5..3] - (RW) alpha value for BW20 (state = 1)
    CR_RDD2_HPF_ALPHA_BW40_0[8..6] - (RW) alpha value for BW40
    CR_RDD2_HPF_ALPHA_BW40_1[11..9] - (RW) alpha value for BW40 (state = 1)
    CR_RDD2_HPF_STATE_CNT_TH[14..12] - (RW) HPF state counter threshold for state = 1
    CR_RDD2_ACI_IGNORE_DC[15]    - (RW) Ignore DC when ACI
    CR_RDD2_HPF_ALPHA_BW80_0[18..16] - (RW) alpha value for BW80
    CR_RDD2_HPF_ALPHA_BW80_1[21..19] - (RW) alpha value for BW80 (state = 1)
    CR_RDD2_HPF_ALPHA_BW160_0[24..22] - (RW) alpha value for BW160
    CR_RDD2_HPF_ALPHA_BW160_1[27..25] - (RW) alpha value for BW160 (state = 1)
    CR_RDD2_GSWITCH_SETTLE_PRD[30..28] - (RW) agc gain switch settling period
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_GSWITCH_SETTLE_PRD_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_GSWITCH_SETTLE_PRD_MASK 0x70000000                // CR_RDD2_GSWITCH_SETTLE_PRD[30..28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_GSWITCH_SETTLE_PRD_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW160_1_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW160_1_MASK 0x0E000000                // CR_RDD2_HPF_ALPHA_BW160_1[27..25]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW160_1_SHFT 25
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW160_0_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW160_0_MASK 0x01C00000                // CR_RDD2_HPF_ALPHA_BW160_0[24..22]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW160_0_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW80_1_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW80_1_MASK 0x00380000                // CR_RDD2_HPF_ALPHA_BW80_1[21..19]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW80_1_SHFT 19
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW80_0_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW80_0_MASK 0x00070000                // CR_RDD2_HPF_ALPHA_BW80_0[18..16]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW80_0_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_ACI_IGNORE_DC_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_ACI_IGNORE_DC_MASK 0x00008000                // CR_RDD2_ACI_IGNORE_DC[15]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_ACI_IGNORE_DC_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_STATE_CNT_TH_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_STATE_CNT_TH_MASK 0x00007000                // CR_RDD2_HPF_STATE_CNT_TH[14..12]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_STATE_CNT_TH_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW40_1_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW40_1_MASK 0x00000E00                // CR_RDD2_HPF_ALPHA_BW40_1[11..9]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW40_1_SHFT 9
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW40_0_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW40_0_MASK 0x000001C0                // CR_RDD2_HPF_ALPHA_BW40_0[8..6]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW40_0_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW20_1_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW20_1_MASK 0x00000038                // CR_RDD2_HPF_ALPHA_BW20_1[5..3]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW20_1_SHFT 3
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW20_0_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW20_0_MASK 0x00000007                // CR_RDD2_HPF_ALPHA_BW20_0[2..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_0_CR_RDD2_HPF_ALPHA_BW20_0_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_1 (0x82000000 + 0x2C54)---

    CR_RDD2_DELTA_RSSI_AACI_TH[4..0] - (RW) delta rssi thrshold for AACI
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD2_DELTA_RSSI_ACI_TH[12..8] - (RW) delta rssi thrshold for ACI
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_RDD2_MIN_VALID_RSSI_WB_DBV[22..16] - (RW) min RSSI ib value for aci detection
    RESERVED23[23]               - (RO) Reserved bits
    CR_RDD2_MAX_VALID_RSSI_IB_DBV[30..24] - (RW) max RSSI ib value for aci detection
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_MAX_VALID_RSSI_IB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_MAX_VALID_RSSI_IB_DBV_MASK 0x7F000000                // CR_RDD2_MAX_VALID_RSSI_IB_DBV[30..24]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_MAX_VALID_RSSI_IB_DBV_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_MIN_VALID_RSSI_WB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_MIN_VALID_RSSI_WB_DBV_MASK 0x007F0000                // CR_RDD2_MIN_VALID_RSSI_WB_DBV[22..16]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_MIN_VALID_RSSI_WB_DBV_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_DELTA_RSSI_ACI_TH_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_DELTA_RSSI_ACI_TH_MASK 0x00001F00                // CR_RDD2_DELTA_RSSI_ACI_TH[12..8]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_DELTA_RSSI_ACI_TH_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_DELTA_RSSI_AACI_TH_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_DELTA_RSSI_AACI_TH_MASK 0x0000001F                // CR_RDD2_DELTA_RSSI_AACI_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_1_CR_RDD2_DELTA_RSSI_AACI_TH_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_2 (0x82000000 + 0x2C58)---

    CR_RDD2_DELTA_RSSI_0_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_RDD2_DELTA_RSSI_1_TH_ACI[11..6] - (RW) delta rssi threshold when aci_det =1
    CR_RDD2_AMSC_FAIL_RATIO_ACI[15..12] - (RW) ratio of amplitude stability check when aci_det =1
    CR_RDD2_DELTA_RSSI_0_TH_SEN[21..16] - (RW) delta rssi threshold when aci_det =0
    CR_RDD2_DELTA_RSSI_1_TH_SEN[27..22] - (RW) delta rssi threshold when aci_det =0
    CR_RDD2_AMSC_FAIL_RATIO_SEN[31..28] - (RW) ratio of amplitude stability check when aci_det =0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_AMSC_FAIL_RATIO_SEN_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_AMSC_FAIL_RATIO_SEN_MASK 0xF0000000                // CR_RDD2_AMSC_FAIL_RATIO_SEN[31..28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_AMSC_FAIL_RATIO_SEN_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_1_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_1_TH_SEN_MASK 0x0FC00000                // CR_RDD2_DELTA_RSSI_1_TH_SEN[27..22]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_1_TH_SEN_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_0_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_0_TH_SEN_MASK 0x003F0000                // CR_RDD2_DELTA_RSSI_0_TH_SEN[21..16]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_0_TH_SEN_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_AMSC_FAIL_RATIO_ACI_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_AMSC_FAIL_RATIO_ACI_MASK 0x0000F000                // CR_RDD2_AMSC_FAIL_RATIO_ACI[15..12]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_AMSC_FAIL_RATIO_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_1_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_1_TH_ACI_MASK 0x00000FC0                // CR_RDD2_DELTA_RSSI_1_TH_ACI[11..6]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_1_TH_ACI_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_0_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_0_TH_ACI_MASK 0x0000003F                // CR_RDD2_DELTA_RSSI_0_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_2_CR_RDD2_DELTA_RSSI_0_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_3 (0x82000000 + 0x2C5C)---

    CR_RDD2_DELTA_RSSI_2_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_RDD2_DELTA_RSSI_2_TH_SEN[11..6] - (RW) delta rssi threshold when aci_det =0
    CR_RDD2_NO_RISE_EDGE_FIX_GAIN_ENB[12] - (RW) no edge detection when agc fix gain
    CR_RDD2_FIRST_RISE_EDGE_ENB[13] - (RW) enable first rise edge as pulse
    RESERVED14[14]               - (RO) Reserved bits
    CR_RDD2_MAX_PULSE_WIDTH[23..15] - (RW) maximum pulse width
    CR_RDD2_MIN_RSSI_DBM[31..24] - (RW) mininum rssi_dbm value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_MIN_RSSI_DBM_ADDR  WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_MIN_RSSI_DBM_MASK  0xFF000000                // CR_RDD2_MIN_RSSI_DBM[31..24]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_MIN_RSSI_DBM_SHFT  24
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_MAX_PULSE_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_MAX_PULSE_WIDTH_MASK 0x00FF8000                // CR_RDD2_MAX_PULSE_WIDTH[23..15]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_MAX_PULSE_WIDTH_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_FIRST_RISE_EDGE_ENB_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_FIRST_RISE_EDGE_ENB_MASK 0x00002000                // CR_RDD2_FIRST_RISE_EDGE_ENB[13]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_FIRST_RISE_EDGE_ENB_SHFT 13
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_NO_RISE_EDGE_FIX_GAIN_ENB_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_NO_RISE_EDGE_FIX_GAIN_ENB_MASK 0x00001000                // CR_RDD2_NO_RISE_EDGE_FIX_GAIN_ENB[12]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_NO_RISE_EDGE_FIX_GAIN_ENB_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_DELTA_RSSI_2_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_DELTA_RSSI_2_TH_SEN_MASK 0x00000FC0                // CR_RDD2_DELTA_RSSI_2_TH_SEN[11..6]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_DELTA_RSSI_2_TH_SEN_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_DELTA_RSSI_2_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_DELTA_RSSI_2_TH_ACI_MASK 0x0000003F                // CR_RDD2_DELTA_RSSI_2_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_3_CR_RDD2_DELTA_RSSI_2_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_4 (0x82000000 + 0x2C60)---

    CR_RDD2_SC_DROP_RATIO[3..0]  - (RW) stability drop ration
    CR_RDD2_SC_CHECK_CNT_DROP[9..4] - (RW) stability check counter value for drop
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_RDD2_SC_PASS_RATIO[15..12] - (RW) stability pass ratio
    CR_RDD2_SC_CHECK_CNT_PASS[21..16] - (RW) stability check counter value for pass
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_RDD2_MIN_PULSE_POWER[31..24] - (RW) mininum pulse power

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_MIN_PULSE_POWER_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_MIN_PULSE_POWER_MASK 0xFF000000                // CR_RDD2_MIN_PULSE_POWER[31..24]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_MIN_PULSE_POWER_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_CHECK_CNT_PASS_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_CHECK_CNT_PASS_MASK 0x003F0000                // CR_RDD2_SC_CHECK_CNT_PASS[21..16]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_CHECK_CNT_PASS_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_PASS_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_PASS_RATIO_MASK 0x0000F000                // CR_RDD2_SC_PASS_RATIO[15..12]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_PASS_RATIO_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_CHECK_CNT_DROP_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_CHECK_CNT_DROP_MASK 0x000003F0                // CR_RDD2_SC_CHECK_CNT_DROP[9..4]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_CHECK_CNT_DROP_SHFT 4
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_DROP_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_DROP_RATIO_MASK 0x0000000F                // CR_RDD2_SC_DROP_RATIO[3..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_4_CR_RDD2_SC_DROP_RATIO_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_5 (0x82000000 + 0x2C64)---

    CR_RDD2_WAKE_UP_PERIOD[7..0] - (RW) send wake up IRQ after this value * 0.8192 ms
    CR_RDD2_WAKE_UP_PULSE_NUM[12..8] - (RW) send wake up IRQ when pulse number exceed this value
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_RDD2_NO_DET_PULSE_PERIOD[20..16] - (RW) send SW reset if no det_pulse during this value * 0.84 sec
    RESERVED21[21]               - (RO) Reserved bits
    CR_RDD2_ERROR_IRQ_EN[22]     - (RW) Enable interrupt (IRQ) when RDD wake up
    CR_RDD2_WAKEUP_IRQ_EN[23]    - (RW) Enable interrupt (IRQ) when RDD error
    CR_RDD2_PULSE_BUF_SEL[27..24] - (RW) select read out pulse number
    CR_RDD2_PULSE_BUF_CLR[28]    - (RW) clear pulse buffer and reset to 0
    RESERVED29[29]               - (RO) Reserved bits
    CR_RDD2_TEST_DET_PULSE[30]   - (RW) Manually generate pulse rise edge
    CR_RDD2_TEST_PULSE_EN[31]    - (RW) Send 32'haaaa_bbbb & 32'hcccc_dddd to AHB wrapper

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_TEST_PULSE_EN_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_TEST_PULSE_EN_MASK 0x80000000                // CR_RDD2_TEST_PULSE_EN[31]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_TEST_PULSE_EN_SHFT 31
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_TEST_DET_PULSE_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_TEST_DET_PULSE_MASK 0x40000000                // CR_RDD2_TEST_DET_PULSE[30]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_TEST_DET_PULSE_SHFT 30
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_PULSE_BUF_CLR_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_PULSE_BUF_CLR_MASK 0x10000000                // CR_RDD2_PULSE_BUF_CLR[28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_PULSE_BUF_CLR_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_PULSE_BUF_SEL_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_PULSE_BUF_SEL_MASK 0x0F000000                // CR_RDD2_PULSE_BUF_SEL[27..24]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_PULSE_BUF_SEL_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKEUP_IRQ_EN_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKEUP_IRQ_EN_MASK 0x00800000                // CR_RDD2_WAKEUP_IRQ_EN[23]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKEUP_IRQ_EN_SHFT 23
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_ERROR_IRQ_EN_ADDR  WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_ERROR_IRQ_EN_MASK  0x00400000                // CR_RDD2_ERROR_IRQ_EN[22]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_ERROR_IRQ_EN_SHFT  22
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_NO_DET_PULSE_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_NO_DET_PULSE_PERIOD_MASK 0x001F0000                // CR_RDD2_NO_DET_PULSE_PERIOD[20..16]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_NO_DET_PULSE_PERIOD_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKE_UP_PULSE_NUM_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKE_UP_PULSE_NUM_MASK 0x00001F00                // CR_RDD2_WAKE_UP_PULSE_NUM[12..8]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKE_UP_PULSE_NUM_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKE_UP_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKE_UP_PERIOD_MASK 0x000000FF                // CR_RDD2_WAKE_UP_PERIOD[7..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_5_CR_RDD2_WAKE_UP_PERIOD_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_6 (0x82000000 + 0x2C68)---

    RO_RDD2_PULSE_BUF_NUM[4..0]  - (RO) Number of pulses stored in buffer
    RESERVED5[7..5]              - (RO) Reserved bits
    RO_RDD2_WAKEUP_IRQ[8]        - (RO) RDD wake up interrupt
    RO_RDD2_ERROR_IRQ[9]         - (RO) RDD error interrupt
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_ERROR_IRQ_ADDR     WF_PHYRX_CTRL_CR_RDD2_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_ERROR_IRQ_MASK     0x00000200                // RO_RDD2_ERROR_IRQ[9]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_ERROR_IRQ_SHFT     9
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_WAKEUP_IRQ_ADDR    WF_PHYRX_CTRL_CR_RDD2_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_WAKEUP_IRQ_MASK    0x00000100                // RO_RDD2_WAKEUP_IRQ[8]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_WAKEUP_IRQ_SHFT    8
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_PULSE_BUF_NUM_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_PULSE_BUF_NUM_MASK 0x0000001F                // RO_RDD2_PULSE_BUF_NUM[4..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_6_RO_RDD2_PULSE_BUF_NUM_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_7 (0x82000000 + 0x2C6C)---

    RO_RDD2_PULSE_BUF_MSB[31..0] - (RO) Read out pulse data for FPGA debug (MSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_7_RO_RDD2_PULSE_BUF_MSB_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_7_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_7_RO_RDD2_PULSE_BUF_MSB_MASK 0xFFFFFFFF                // RO_RDD2_PULSE_BUF_MSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_7_RO_RDD2_PULSE_BUF_MSB_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_8 (0x82000000 + 0x2C70)---

    RO_RDD2_PULSE_BUF_LSB[31..0] - (RO) Read out pulse data for FPGA debug (LSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_8_RO_RDD2_PULSE_BUF_LSB_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_8_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_8_RO_RDD2_PULSE_BUF_LSB_MASK 0xFFFFFFFF                // RO_RDD2_PULSE_BUF_LSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_8_RO_RDD2_PULSE_BUF_LSB_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_12 (0x82000000 + 0x2C80)---

    CR_RDD2_MDRDY_START[6..0]    - (RW) RDD MDRDY start time
    CR_RDD2_MDRDY_END[13..7]     - (RW) RDD MDRDY end time
    CR_RDD2_MDRDY_SEL[14]        - (RW) MDRDY select, 0: MDRDY raising, 1: MDRDY trigger
    RESERVED15[26..15]           - (RO) Reserved bits
    CR_RDD2_CCA_SEL[28..27]      - (RW) [DE] BBP control CR
    CR_RDD2_BAND_SEL[29]         - (RW) [DE] BBP control CR
    CR_RDD2_ANT_SEL[31..30]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_ANT_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_ANT_SEL_MASK      0xC0000000                // CR_RDD2_ANT_SEL[31..30]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_ANT_SEL_SHFT      30
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_BAND_SEL_ADDR     WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_BAND_SEL_MASK     0x20000000                // CR_RDD2_BAND_SEL[29]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_BAND_SEL_SHFT     29
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_CCA_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_CCA_SEL_MASK      0x18000000                // CR_RDD2_CCA_SEL[28..27]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_CCA_SEL_SHFT      27
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_SEL_ADDR    WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_SEL_MASK    0x00004000                // CR_RDD2_MDRDY_SEL[14]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_SEL_SHFT    14
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_END_ADDR    WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_END_MASK    0x00003F80                // CR_RDD2_MDRDY_END[13..7]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_END_SHFT    7
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_START_ADDR  WF_PHYRX_CTRL_CR_RDD2_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_START_MASK  0x0000007F                // CR_RDD2_MDRDY_START[6..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_12_CR_RDD2_MDRDY_START_SHFT  0

/* =====================================================================================

  ---CR_RDD2_TOP_13 (0x82000000 + 0x2C84)---

    CR_RDD2_DC_RATIO_TH[4..0]    - (RW) dc pulse cnt ratio
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD2_MIN_RSSI_0_DBV_FOR_ED[14..8] - (RW) DBV for ED
    RESERVED15[20..15]           - (RO) Reserved bits
    CR_RDD2_ACI_EXIST_RATIO[25..21] - (RW) cr ACI exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD2_DISA_2BST[28]        - (RW) 1: Disable only one 2nd subband exist
                                     it means we can hold 3 subband as high
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_DISA_2BST_ADDR    WF_PHYRX_CTRL_CR_RDD2_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_DISA_2BST_MASK    0x10000000                // CR_RDD2_DISA_2BST[28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_DISA_2BST_SHFT    28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_ACI_EXIST_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_ACI_EXIST_RATIO_MASK 0x03E00000                // CR_RDD2_ACI_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_ACI_EXIST_RATIO_SHFT 21
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_MIN_RSSI_0_DBV_FOR_ED_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_MIN_RSSI_0_DBV_FOR_ED_MASK 0x00007F00                // CR_RDD2_MIN_RSSI_0_DBV_FOR_ED[14..8]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_MIN_RSSI_0_DBV_FOR_ED_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_DC_RATIO_TH_ADDR  WF_PHYRX_CTRL_CR_RDD2_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_DC_RATIO_TH_MASK  0x0000001F                // CR_RDD2_DC_RATIO_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_13_CR_RDD2_DC_RATIO_TH_SHFT  0

/* =====================================================================================

  ---CR_RDD2_TOP_14 (0x82000000 + 0x2C88)---

    CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0] - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12] - (RW) min cnt of ACI
    CR_RDD2_DC_EXIST_RATIO[25..21] - (RW) cr dc exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD2_RSSI_MAX_2ND_DIFF[31..28] - (RW) subband RSSI comparison,
                                     max subband and 2nd subband threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_RSSI_MAX_2ND_DIFF_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_RSSI_MAX_2ND_DIFF_MASK 0xF0000000                // CR_RDD2_RSSI_MAX_2ND_DIFF[31..28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_RSSI_MAX_2ND_DIFF_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_DC_EXIST_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_DC_EXIST_RATIO_MASK 0x03E00000                // CR_RDD2_DC_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_DC_EXIST_RATIO_SHFT 21
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_MASK 0x001FF000                // CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_MASK 0x000001FF                // CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_14_CR_RDD2_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_15 (0x82000000 + 0x2C8C)---

    CR_RDD2_MIN_LP_WIDTH[8..0]   - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_RDD2_MAX_PP_WIDTH[20..12] - (RW) min cnt of ACI
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_RDD2_ACI_CNT_AACI[27..24] - (RW) aaci initial value
    CR_RDD2_ACI_CNT_MAX[31..28]  - (RW) aci maxinum value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_ACI_CNT_MAX_ADDR  WF_PHYRX_CTRL_CR_RDD2_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_ACI_CNT_MAX_MASK  0xF0000000                // CR_RDD2_ACI_CNT_MAX[31..28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_ACI_CNT_MAX_SHFT  28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_ACI_CNT_AACI_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_ACI_CNT_AACI_MASK 0x0F000000                // CR_RDD2_ACI_CNT_AACI[27..24]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_ACI_CNT_AACI_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_MAX_PP_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_MAX_PP_WIDTH_MASK 0x001FF000                // CR_RDD2_MAX_PP_WIDTH[20..12]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_MAX_PP_WIDTH_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_MIN_LP_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_MIN_LP_WIDTH_MASK 0x000001FF                // CR_RDD2_MIN_LP_WIDTH[8..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_15_CR_RDD2_MIN_LP_WIDTH_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_16 (0x82000000 + 0x2C90)---

    CR_RDD2_ACI_CHECK_PRD[4..0]  - (RW) accumulation period times of RSSI update
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD2_CNT_ACI_DET_DROP[12..8] - (RW) threshold for detction of ACI times per 4us
    RESERVED13[19..13]           - (RO) Reserved bits
    CR_RDD2_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20] - (RW) count for aci min pulse check
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_MAX_PULSE_WIDTH_DO_ACI_CHECK_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_MAX_PULSE_WIDTH_DO_ACI_CHECK_MASK 0x1FF00000                // CR_RDD2_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_MAX_PULSE_WIDTH_DO_ACI_CHECK_SHFT 20
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_CNT_ACI_DET_DROP_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_CNT_ACI_DET_DROP_MASK 0x00001F00                // CR_RDD2_CNT_ACI_DET_DROP[12..8]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_CNT_ACI_DET_DROP_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_ACI_CHECK_PRD_ADDR WF_PHYRX_CTRL_CR_RDD2_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_ACI_CHECK_PRD_MASK 0x0000001F                // CR_RDD2_ACI_CHECK_PRD[4..0]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_16_CR_RDD2_ACI_CHECK_PRD_SHFT 0

/* =====================================================================================

  ---CR_RDD2_TOP_17 (0x82000000 + 0x2C94)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_RDD2_ACI_CNT_L[27..24]    - (RW) aci_cnt threshold
    CR_RDD2_ACI_CNT_H[31..28]    - (RW) aci_cnt threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_CR_RDD2_ACI_CNT_H_ADDR    WF_PHYRX_CTRL_CR_RDD2_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_CR_RDD2_ACI_CNT_H_MASK    0xF0000000                // CR_RDD2_ACI_CNT_H[31..28]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_CR_RDD2_ACI_CNT_H_SHFT    28
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_CR_RDD2_ACI_CNT_L_ADDR    WF_PHYRX_CTRL_CR_RDD2_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_CR_RDD2_ACI_CNT_L_MASK    0x0F000000                // CR_RDD2_ACI_CNT_L[27..24]
#define WF_PHYRX_CTRL_CR_RDD2_TOP_17_CR_RDD2_ACI_CNT_L_SHFT    24

/* =====================================================================================

  ---CR_RDD3_TOP_0 (0x82000000 + 0x2CA0)---

    CR_RDD3_HPF_ALPHA_BW20_0[2..0] - (RW) alpha value for BW20
    CR_RDD3_HPF_ALPHA_BW20_1[5..3] - (RW) alpha value for BW20 (state = 1)
    CR_RDD3_HPF_ALPHA_BW40_0[8..6] - (RW) alpha value for BW40
    CR_RDD3_HPF_ALPHA_BW40_1[11..9] - (RW) alpha value for BW40 (state = 1)
    CR_RDD3_HPF_STATE_CNT_TH[14..12] - (RW) HPF state counter threshold for state = 1
    CR_RDD3_ACI_IGNORE_DC[15]    - (RW) Ignore DC when ACI
    CR_RDD3_HPF_ALPHA_BW80_0[18..16] - (RW) alpha value for BW80
    CR_RDD3_HPF_ALPHA_BW80_1[21..19] - (RW) alpha value for BW80 (state = 1)
    CR_RDD3_HPF_ALPHA_BW160_0[24..22] - (RW) alpha value for BW160
    CR_RDD3_HPF_ALPHA_BW160_1[27..25] - (RW) alpha value for BW160 (state = 1)
    CR_RDD3_GSWITCH_SETTLE_PRD[30..28] - (RW) agc gain switch settling period
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_GSWITCH_SETTLE_PRD_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_GSWITCH_SETTLE_PRD_MASK 0x70000000                // CR_RDD3_GSWITCH_SETTLE_PRD[30..28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_GSWITCH_SETTLE_PRD_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW160_1_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW160_1_MASK 0x0E000000                // CR_RDD3_HPF_ALPHA_BW160_1[27..25]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW160_1_SHFT 25
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW160_0_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW160_0_MASK 0x01C00000                // CR_RDD3_HPF_ALPHA_BW160_0[24..22]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW160_0_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW80_1_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW80_1_MASK 0x00380000                // CR_RDD3_HPF_ALPHA_BW80_1[21..19]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW80_1_SHFT 19
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW80_0_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW80_0_MASK 0x00070000                // CR_RDD3_HPF_ALPHA_BW80_0[18..16]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW80_0_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_ACI_IGNORE_DC_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_ACI_IGNORE_DC_MASK 0x00008000                // CR_RDD3_ACI_IGNORE_DC[15]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_ACI_IGNORE_DC_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_STATE_CNT_TH_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_STATE_CNT_TH_MASK 0x00007000                // CR_RDD3_HPF_STATE_CNT_TH[14..12]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_STATE_CNT_TH_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW40_1_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW40_1_MASK 0x00000E00                // CR_RDD3_HPF_ALPHA_BW40_1[11..9]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW40_1_SHFT 9
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW40_0_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW40_0_MASK 0x000001C0                // CR_RDD3_HPF_ALPHA_BW40_0[8..6]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW40_0_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW20_1_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW20_1_MASK 0x00000038                // CR_RDD3_HPF_ALPHA_BW20_1[5..3]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW20_1_SHFT 3
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW20_0_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_0_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW20_0_MASK 0x00000007                // CR_RDD3_HPF_ALPHA_BW20_0[2..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_0_CR_RDD3_HPF_ALPHA_BW20_0_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_1 (0x82000000 + 0x2CA4)---

    CR_RDD3_DELTA_RSSI_AACI_TH[4..0] - (RW) delta rssi thrshold for AACI
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD3_DELTA_RSSI_ACI_TH[12..8] - (RW) delta rssi thrshold for ACI
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_RDD3_MIN_VALID_RSSI_WB_DBV[22..16] - (RW) min RSSI ib value for aci detection
    RESERVED23[23]               - (RO) Reserved bits
    CR_RDD3_MAX_VALID_RSSI_IB_DBV[30..24] - (RW) max RSSI ib value for aci detection
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_MAX_VALID_RSSI_IB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_MAX_VALID_RSSI_IB_DBV_MASK 0x7F000000                // CR_RDD3_MAX_VALID_RSSI_IB_DBV[30..24]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_MAX_VALID_RSSI_IB_DBV_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_MIN_VALID_RSSI_WB_DBV_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_MIN_VALID_RSSI_WB_DBV_MASK 0x007F0000                // CR_RDD3_MIN_VALID_RSSI_WB_DBV[22..16]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_MIN_VALID_RSSI_WB_DBV_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_DELTA_RSSI_ACI_TH_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_DELTA_RSSI_ACI_TH_MASK 0x00001F00                // CR_RDD3_DELTA_RSSI_ACI_TH[12..8]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_DELTA_RSSI_ACI_TH_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_DELTA_RSSI_AACI_TH_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_1_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_DELTA_RSSI_AACI_TH_MASK 0x0000001F                // CR_RDD3_DELTA_RSSI_AACI_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_1_CR_RDD3_DELTA_RSSI_AACI_TH_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_2 (0x82000000 + 0x2CA8)---

    CR_RDD3_DELTA_RSSI_0_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_RDD3_DELTA_RSSI_1_TH_ACI[11..6] - (RW) delta rssi threshold when aci_det =1
    CR_RDD3_AMSC_FAIL_RATIO_ACI[15..12] - (RW) ratio of amplitude stability check when aci_det =1
    CR_RDD3_DELTA_RSSI_0_TH_SEN[21..16] - (RW) delta rssi threshold when aci_det =0
    CR_RDD3_DELTA_RSSI_1_TH_SEN[27..22] - (RW) delta rssi threshold when aci_det =0
    CR_RDD3_AMSC_FAIL_RATIO_SEN[31..28] - (RW) ratio of amplitude stability check when aci_det =0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_AMSC_FAIL_RATIO_SEN_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_AMSC_FAIL_RATIO_SEN_MASK 0xF0000000                // CR_RDD3_AMSC_FAIL_RATIO_SEN[31..28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_AMSC_FAIL_RATIO_SEN_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_1_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_1_TH_SEN_MASK 0x0FC00000                // CR_RDD3_DELTA_RSSI_1_TH_SEN[27..22]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_1_TH_SEN_SHFT 22
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_0_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_0_TH_SEN_MASK 0x003F0000                // CR_RDD3_DELTA_RSSI_0_TH_SEN[21..16]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_0_TH_SEN_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_AMSC_FAIL_RATIO_ACI_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_AMSC_FAIL_RATIO_ACI_MASK 0x0000F000                // CR_RDD3_AMSC_FAIL_RATIO_ACI[15..12]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_AMSC_FAIL_RATIO_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_1_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_1_TH_ACI_MASK 0x00000FC0                // CR_RDD3_DELTA_RSSI_1_TH_ACI[11..6]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_1_TH_ACI_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_0_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_2_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_0_TH_ACI_MASK 0x0000003F                // CR_RDD3_DELTA_RSSI_0_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_2_CR_RDD3_DELTA_RSSI_0_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_3 (0x82000000 + 0x2CAC)---

    CR_RDD3_DELTA_RSSI_2_TH_ACI[5..0] - (RW) delta rssi threshold when aci_det =1
    CR_RDD3_DELTA_RSSI_2_TH_SEN[11..6] - (RW) delta rssi threshold when aci_det =0
    CR_RDD3_NO_RISE_EDGE_FIX_GAIN_ENB[12] - (RW) no edge detection when agc fix gain
    CR_RDD3_FIRST_RISE_EDGE_ENB[13] - (RW) enable first rise edge as pulse
    RESERVED14[14]               - (RO) Reserved bits
    CR_RDD3_MAX_PULSE_WIDTH[23..15] - (RW) maximum pulse width
    CR_RDD3_MIN_RSSI_DBM[31..24] - (RW) mininum rssi_dbm value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_MIN_RSSI_DBM_ADDR  WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_MIN_RSSI_DBM_MASK  0xFF000000                // CR_RDD3_MIN_RSSI_DBM[31..24]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_MIN_RSSI_DBM_SHFT  24
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_MAX_PULSE_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_MAX_PULSE_WIDTH_MASK 0x00FF8000                // CR_RDD3_MAX_PULSE_WIDTH[23..15]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_MAX_PULSE_WIDTH_SHFT 15
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_FIRST_RISE_EDGE_ENB_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_FIRST_RISE_EDGE_ENB_MASK 0x00002000                // CR_RDD3_FIRST_RISE_EDGE_ENB[13]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_FIRST_RISE_EDGE_ENB_SHFT 13
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_NO_RISE_EDGE_FIX_GAIN_ENB_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_NO_RISE_EDGE_FIX_GAIN_ENB_MASK 0x00001000                // CR_RDD3_NO_RISE_EDGE_FIX_GAIN_ENB[12]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_NO_RISE_EDGE_FIX_GAIN_ENB_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_DELTA_RSSI_2_TH_SEN_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_DELTA_RSSI_2_TH_SEN_MASK 0x00000FC0                // CR_RDD3_DELTA_RSSI_2_TH_SEN[11..6]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_DELTA_RSSI_2_TH_SEN_SHFT 6
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_DELTA_RSSI_2_TH_ACI_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_3_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_DELTA_RSSI_2_TH_ACI_MASK 0x0000003F                // CR_RDD3_DELTA_RSSI_2_TH_ACI[5..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_3_CR_RDD3_DELTA_RSSI_2_TH_ACI_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_4 (0x82000000 + 0x2CB0)---

    CR_RDD3_SC_DROP_RATIO[3..0]  - (RW) stability drop ration
    CR_RDD3_SC_CHECK_CNT_DROP[9..4] - (RW) stability check counter value for drop
    RESERVED10[11..10]           - (RO) Reserved bits
    CR_RDD3_SC_PASS_RATIO[15..12] - (RW) stability pass ratio
    CR_RDD3_SC_CHECK_CNT_PASS[21..16] - (RW) stability check counter value for pass
    RESERVED22[23..22]           - (RO) Reserved bits
    CR_RDD3_MIN_PULSE_POWER[31..24] - (RW) mininum pulse power

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_MIN_PULSE_POWER_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_MIN_PULSE_POWER_MASK 0xFF000000                // CR_RDD3_MIN_PULSE_POWER[31..24]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_MIN_PULSE_POWER_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_CHECK_CNT_PASS_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_CHECK_CNT_PASS_MASK 0x003F0000                // CR_RDD3_SC_CHECK_CNT_PASS[21..16]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_CHECK_CNT_PASS_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_PASS_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_PASS_RATIO_MASK 0x0000F000                // CR_RDD3_SC_PASS_RATIO[15..12]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_PASS_RATIO_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_CHECK_CNT_DROP_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_CHECK_CNT_DROP_MASK 0x000003F0                // CR_RDD3_SC_CHECK_CNT_DROP[9..4]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_CHECK_CNT_DROP_SHFT 4
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_DROP_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_4_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_DROP_RATIO_MASK 0x0000000F                // CR_RDD3_SC_DROP_RATIO[3..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_4_CR_RDD3_SC_DROP_RATIO_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_5 (0x82000000 + 0x2CB4)---

    CR_RDD3_WAKE_UP_PERIOD[7..0] - (RW) send wake up IRQ after this value * 0.8192 ms
    CR_RDD3_WAKE_UP_PULSE_NUM[12..8] - (RW) send wake up IRQ when pulse number exceed this value
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_RDD3_NO_DET_PULSE_PERIOD[20..16] - (RW) send SW reset if no det_pulse during this value * 0.84 sec
    RESERVED21[21]               - (RO) Reserved bits
    CR_RDD3_ERROR_IRQ_EN[22]     - (RW) Enable interrupt (IRQ) when RDD wake up
    CR_RDD3_WAKEUP_IRQ_EN[23]    - (RW) Enable interrupt (IRQ) when RDD error
    CR_RDD3_PULSE_BUF_SEL[27..24] - (RW) select read out pulse number
    CR_RDD3_PULSE_BUF_CLR[28]    - (RW) clear pulse buffer and reset to 0
    RESERVED29[29]               - (RO) Reserved bits
    CR_RDD3_TEST_DET_PULSE[30]   - (RW) Manually generate pulse rise edge
    CR_RDD3_TEST_PULSE_EN[31]    - (RW) Send 32'haaaa_bbbb & 32'hcccc_dddd to AHB wrapper

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_TEST_PULSE_EN_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_TEST_PULSE_EN_MASK 0x80000000                // CR_RDD3_TEST_PULSE_EN[31]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_TEST_PULSE_EN_SHFT 31
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_TEST_DET_PULSE_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_TEST_DET_PULSE_MASK 0x40000000                // CR_RDD3_TEST_DET_PULSE[30]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_TEST_DET_PULSE_SHFT 30
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_PULSE_BUF_CLR_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_PULSE_BUF_CLR_MASK 0x10000000                // CR_RDD3_PULSE_BUF_CLR[28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_PULSE_BUF_CLR_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_PULSE_BUF_SEL_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_PULSE_BUF_SEL_MASK 0x0F000000                // CR_RDD3_PULSE_BUF_SEL[27..24]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_PULSE_BUF_SEL_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKEUP_IRQ_EN_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKEUP_IRQ_EN_MASK 0x00800000                // CR_RDD3_WAKEUP_IRQ_EN[23]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKEUP_IRQ_EN_SHFT 23
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_ERROR_IRQ_EN_ADDR  WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_ERROR_IRQ_EN_MASK  0x00400000                // CR_RDD3_ERROR_IRQ_EN[22]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_ERROR_IRQ_EN_SHFT  22
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_NO_DET_PULSE_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_NO_DET_PULSE_PERIOD_MASK 0x001F0000                // CR_RDD3_NO_DET_PULSE_PERIOD[20..16]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_NO_DET_PULSE_PERIOD_SHFT 16
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKE_UP_PULSE_NUM_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKE_UP_PULSE_NUM_MASK 0x00001F00                // CR_RDD3_WAKE_UP_PULSE_NUM[12..8]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKE_UP_PULSE_NUM_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKE_UP_PERIOD_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_5_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKE_UP_PERIOD_MASK 0x000000FF                // CR_RDD3_WAKE_UP_PERIOD[7..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_5_CR_RDD3_WAKE_UP_PERIOD_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_6 (0x82000000 + 0x2CB8)---

    RO_RDD3_PULSE_BUF_NUM[4..0]  - (RO) Number of pulses stored in buffer
    RESERVED5[7..5]              - (RO) Reserved bits
    RO_RDD3_WAKEUP_IRQ[8]        - (RO) RDD wake up interrupt
    RO_RDD3_ERROR_IRQ[9]         - (RO) RDD error interrupt
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_ERROR_IRQ_ADDR     WF_PHYRX_CTRL_CR_RDD3_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_ERROR_IRQ_MASK     0x00000200                // RO_RDD3_ERROR_IRQ[9]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_ERROR_IRQ_SHFT     9
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_WAKEUP_IRQ_ADDR    WF_PHYRX_CTRL_CR_RDD3_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_WAKEUP_IRQ_MASK    0x00000100                // RO_RDD3_WAKEUP_IRQ[8]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_WAKEUP_IRQ_SHFT    8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_PULSE_BUF_NUM_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_6_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_PULSE_BUF_NUM_MASK 0x0000001F                // RO_RDD3_PULSE_BUF_NUM[4..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_6_RO_RDD3_PULSE_BUF_NUM_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_7 (0x82000000 + 0x2CBC)---

    RO_RDD3_PULSE_BUF_MSB[31..0] - (RO) Read out pulse data for FPGA debug (MSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_7_RO_RDD3_PULSE_BUF_MSB_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_7_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_7_RO_RDD3_PULSE_BUF_MSB_MASK 0xFFFFFFFF                // RO_RDD3_PULSE_BUF_MSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_7_RO_RDD3_PULSE_BUF_MSB_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_8 (0x82000000 + 0x2CC0)---

    RO_RDD3_PULSE_BUF_LSB[31..0] - (RO) Read out pulse data for FPGA debug (LSB)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_8_RO_RDD3_PULSE_BUF_LSB_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_8_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_8_RO_RDD3_PULSE_BUF_LSB_MASK 0xFFFFFFFF                // RO_RDD3_PULSE_BUF_LSB[31..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_8_RO_RDD3_PULSE_BUF_LSB_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_12 (0x82000000 + 0x2CC4)---

    CR_RDD3_MDRDY_START[6..0]    - (RW) RDD MDRDY start time
    CR_RDD3_MDRDY_END[13..7]     - (RW) RDD MDRDY end time
    CR_RDD3_MDRDY_SEL[14]        - (RW) MDRDY select, 0: MDRDY raising, 1: MDRDY trigger
    RESERVED15[26..15]           - (RO) Reserved bits
    CR_RDD3_CCA_SEL[28..27]      - (RW) [DE] BBP control CR
    CR_RDD3_BAND_SEL[29]         - (RW) [DE] BBP control CR
    CR_RDD3_ANT_SEL[31..30]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_ANT_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_ANT_SEL_MASK      0xC0000000                // CR_RDD3_ANT_SEL[31..30]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_ANT_SEL_SHFT      30
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_BAND_SEL_ADDR     WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_BAND_SEL_MASK     0x20000000                // CR_RDD3_BAND_SEL[29]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_BAND_SEL_SHFT     29
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_CCA_SEL_ADDR      WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_CCA_SEL_MASK      0x18000000                // CR_RDD3_CCA_SEL[28..27]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_CCA_SEL_SHFT      27
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_SEL_ADDR    WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_SEL_MASK    0x00004000                // CR_RDD3_MDRDY_SEL[14]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_SEL_SHFT    14
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_END_ADDR    WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_END_MASK    0x00003F80                // CR_RDD3_MDRDY_END[13..7]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_END_SHFT    7
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_START_ADDR  WF_PHYRX_CTRL_CR_RDD3_TOP_12_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_START_MASK  0x0000007F                // CR_RDD3_MDRDY_START[6..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_12_CR_RDD3_MDRDY_START_SHFT  0

/* =====================================================================================

  ---CR_RDD3_TOP_13 (0x82000000 + 0x2CC8)---

    CR_RDD3_DC_RATIO_TH[4..0]    - (RW) dc pulse cnt ratio
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD3_MIN_RSSI_0_DBV_FOR_ED[14..8] - (RW) DBV for ED
    RESERVED15[20..15]           - (RO) Reserved bits
    CR_RDD3_ACI_EXIST_RATIO[25..21] - (RW) cr ACI exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD3_DISA_2BST[28]        - (RW) 1: Disable only one 2nd subband exist
                                     it means we can hold 3 subband as high
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_DISA_2BST_ADDR    WF_PHYRX_CTRL_CR_RDD3_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_DISA_2BST_MASK    0x10000000                // CR_RDD3_DISA_2BST[28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_DISA_2BST_SHFT    28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_ACI_EXIST_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_ACI_EXIST_RATIO_MASK 0x03E00000                // CR_RDD3_ACI_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_ACI_EXIST_RATIO_SHFT 21
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_MIN_RSSI_0_DBV_FOR_ED_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_MIN_RSSI_0_DBV_FOR_ED_MASK 0x00007F00                // CR_RDD3_MIN_RSSI_0_DBV_FOR_ED[14..8]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_MIN_RSSI_0_DBV_FOR_ED_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_DC_RATIO_TH_ADDR  WF_PHYRX_CTRL_CR_RDD3_TOP_13_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_DC_RATIO_TH_MASK  0x0000001F                // CR_RDD3_DC_RATIO_TH[4..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_13_CR_RDD3_DC_RATIO_TH_SHFT  0

/* =====================================================================================

  ---CR_RDD3_TOP_14 (0x82000000 + 0x2CCC)---

    CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0] - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12] - (RW) min cnt of ACI
    CR_RDD3_DC_EXIST_RATIO[25..21] - (RW) cr dc exist count ratio
    RESERVED26[27..26]           - (RO) Reserved bits
    CR_RDD3_RSSI_MAX_2ND_DIFF[31..28] - (RW) subband RSSI comparison,
                                     max subband and 2nd subband threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_RSSI_MAX_2ND_DIFF_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_RSSI_MAX_2ND_DIFF_MASK 0xF0000000                // CR_RDD3_RSSI_MAX_2ND_DIFF[31..28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_RSSI_MAX_2ND_DIFF_SHFT 28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_DC_EXIST_RATIO_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_DC_EXIST_RATIO_MASK 0x03E00000                // CR_RDD3_DC_EXIST_RATIO[25..21]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_DC_EXIST_RATIO_SHFT 21
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_MASK 0x001FF000                // CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI[20..12]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_ACI_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_14_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_MASK 0x000001FF                // CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_DC[8..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_14_CR_RDD3_MIN_NO_GSWITCH_PRD_CNT_FOR_DC_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_15 (0x82000000 + 0x2CD0)---

    CR_RDD3_MIN_LP_WIDTH[8..0]   - (RW) min cnt of DC
    RESERVED9[11..9]             - (RO) Reserved bits
    CR_RDD3_MAX_PP_WIDTH[20..12] - (RW) min cnt of ACI
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_RDD3_ACI_CNT_AACI[27..24] - (RW) aaci initial value
    CR_RDD3_ACI_CNT_MAX[31..28]  - (RW) aci maxinum value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_ACI_CNT_MAX_ADDR  WF_PHYRX_CTRL_CR_RDD3_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_ACI_CNT_MAX_MASK  0xF0000000                // CR_RDD3_ACI_CNT_MAX[31..28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_ACI_CNT_MAX_SHFT  28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_ACI_CNT_AACI_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_ACI_CNT_AACI_MASK 0x0F000000                // CR_RDD3_ACI_CNT_AACI[27..24]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_ACI_CNT_AACI_SHFT 24
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_MAX_PP_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_MAX_PP_WIDTH_MASK 0x001FF000                // CR_RDD3_MAX_PP_WIDTH[20..12]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_MAX_PP_WIDTH_SHFT 12
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_MIN_LP_WIDTH_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_15_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_MIN_LP_WIDTH_MASK 0x000001FF                // CR_RDD3_MIN_LP_WIDTH[8..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_15_CR_RDD3_MIN_LP_WIDTH_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_16 (0x82000000 + 0x2CD4)---

    CR_RDD3_ACI_CHECK_PRD[4..0]  - (RW) accumulation period times of RSSI update
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_RDD3_CNT_ACI_DET_DROP[12..8] - (RW) threshold for detction of ACI times per 4us
    RESERVED13[19..13]           - (RO) Reserved bits
    CR_RDD3_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20] - (RW) count for aci min pulse check
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_MAX_PULSE_WIDTH_DO_ACI_CHECK_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_MAX_PULSE_WIDTH_DO_ACI_CHECK_MASK 0x1FF00000                // CR_RDD3_MAX_PULSE_WIDTH_DO_ACI_CHECK[28..20]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_MAX_PULSE_WIDTH_DO_ACI_CHECK_SHFT 20
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_CNT_ACI_DET_DROP_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_CNT_ACI_DET_DROP_MASK 0x00001F00                // CR_RDD3_CNT_ACI_DET_DROP[12..8]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_CNT_ACI_DET_DROP_SHFT 8
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_ACI_CHECK_PRD_ADDR WF_PHYRX_CTRL_CR_RDD3_TOP_16_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_ACI_CHECK_PRD_MASK 0x0000001F                // CR_RDD3_ACI_CHECK_PRD[4..0]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_16_CR_RDD3_ACI_CHECK_PRD_SHFT 0

/* =====================================================================================

  ---CR_RDD3_TOP_17 (0x82000000 + 0x2CD8)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_RDD3_ACI_CNT_L[27..24]    - (RW) aci_cnt threshold
    CR_RDD3_ACI_CNT_H[31..28]    - (RW) aci_cnt threshold

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_CR_RDD3_ACI_CNT_H_ADDR    WF_PHYRX_CTRL_CR_RDD3_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_CR_RDD3_ACI_CNT_H_MASK    0xF0000000                // CR_RDD3_ACI_CNT_H[31..28]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_CR_RDD3_ACI_CNT_H_SHFT    28
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_CR_RDD3_ACI_CNT_L_ADDR    WF_PHYRX_CTRL_CR_RDD3_TOP_17_ADDR
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_CR_RDD3_ACI_CNT_L_MASK    0x0F000000                // CR_RDD3_ACI_CNT_L[27..24]
#define WF_PHYRX_CTRL_CR_RDD3_TOP_17_CR_RDD3_ACI_CNT_L_SHFT    24

/* =====================================================================================

  ---CR_BAND1_PHY_CTRL_0 (0x82000000 + 0x3000)---

    CR_BAND1_20BW_HT_ACI[0]      - (RW) [DE] BBP control CR
    CR_BAND1_20BW_LG_ACI[1]      - (RW) [DE] BBP control CR
    CR_BAND1_HT_BW_CTRL[3..2]    - (RW) [DE] BBP control CR
    CR_BAND1_LG_BW_CTRL[5..4]    - (RW) [DE] BBP control CR
    CR_BAND1_CCK_ACI_CTRL[6]     - (RW) [DE] BBP control CR
    CR_BAND1_LG_LEN_CTRL[7]      - (RW) [DE] BBP control CR
    CR_BAND1_HT_ACI_CTRL[11..8]  - (RW) [DE] BBP control CR
    CR_BAND1_LG_ACI_CTRL[15..12] - (RW) [DE] BBP control CR
    CR_BAND1_SEC_CH[18..16]      - (RW) [DE] BBP control CR
    RESERVED19[19]               - (RO) Reserved bits
    CR_BAND1_PRI_CH[22..20]      - (RW) [DE] BBP control CR
    RESERVED23[23]               - (RO) Reserved bits
    CR_BAND1_CBW[27..24]         - (RW) [DE] BBP control CR
    CR_BAND1_BAND[30..28]        - (RW) 0: 2G Band
                                     1: 5G Band
                                     2: Japan Mode 10M BW
                                     3: Japan Mode 5M BW
    CR_BAND1_EN[31]              - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_EN_ADDR     WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_EN_MASK     0x80000000                // CR_BAND1_EN[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_EN_SHFT     31
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_BAND_ADDR   WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_BAND_MASK   0x70000000                // CR_BAND1_BAND[30..28]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_BAND_SHFT   28
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_CBW_ADDR    WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_CBW_MASK    0x0F000000                // CR_BAND1_CBW[27..24]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_CBW_SHFT    24
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_PRI_CH_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_PRI_CH_MASK 0x00700000                // CR_BAND1_PRI_CH[22..20]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_PRI_CH_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_SEC_CH_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_SEC_CH_MASK 0x00070000                // CR_BAND1_SEC_CH[18..16]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_SEC_CH_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_ACI_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_ACI_CTRL_MASK 0x0000F000                // CR_BAND1_LG_ACI_CTRL[15..12]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_ACI_CTRL_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_HT_ACI_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_HT_ACI_CTRL_MASK 0x00000F00                // CR_BAND1_HT_ACI_CTRL[11..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_HT_ACI_CTRL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_LEN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_LEN_CTRL_MASK 0x00000080                // CR_BAND1_LG_LEN_CTRL[7]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_LEN_CTRL_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_CCK_ACI_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_CCK_ACI_CTRL_MASK 0x00000040                // CR_BAND1_CCK_ACI_CTRL[6]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_CCK_ACI_CTRL_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_BW_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_BW_CTRL_MASK 0x00000030                // CR_BAND1_LG_BW_CTRL[5..4]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_LG_BW_CTRL_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_HT_BW_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_HT_BW_CTRL_MASK 0x0000000C                // CR_BAND1_HT_BW_CTRL[3..2]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_HT_BW_CTRL_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_20BW_LG_ACI_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_20BW_LG_ACI_MASK 0x00000002                // CR_BAND1_20BW_LG_ACI[1]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_20BW_LG_ACI_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_20BW_HT_ACI_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_20BW_HT_ACI_MASK 0x00000001                // CR_BAND1_20BW_HT_ACI[0]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_0_CR_BAND1_20BW_HT_ACI_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHY_CTRL_1 (0x82000000 + 0x3004)---

    CR_BAND1_HND_VHT_CTRL[7..0]  - (RW) [DE] BBP control CR
    CR_BAND1_HND_LG_CTRL[15..8]  - (RW) [DE] BBP control CR
    CR_BAND1_HND_HT_CTRL[23..16] - (RW) [DE] BBP control CR
    CR_BAND1_HND_CCK_CTRL[27..24] - (RW) [DE] BBP control CR
    CR_BAND1_HND_CTRL[29..28]    - (RW) [DE] BBP control CR
    CR_BAND1_USA_JPN_MODE[30]    - (RW) [DE] BBP control CR
    CR_BAND1_FSM_CTRL[31]        - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_FSM_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_FSM_CTRL_MASK 0x80000000                // CR_BAND1_FSM_CTRL[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_FSM_CTRL_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_USA_JPN_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_USA_JPN_MODE_MASK 0x40000000                // CR_BAND1_USA_JPN_MODE[30]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_USA_JPN_MODE_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_CTRL_MASK 0x30000000                // CR_BAND1_HND_CTRL[29..28]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_CTRL_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_CCK_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_CCK_CTRL_MASK 0x0F000000                // CR_BAND1_HND_CCK_CTRL[27..24]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_CCK_CTRL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_HT_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_HT_CTRL_MASK 0x00FF0000                // CR_BAND1_HND_HT_CTRL[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_HT_CTRL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_LG_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_LG_CTRL_MASK 0x0000FF00                // CR_BAND1_HND_LG_CTRL[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_LG_CTRL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_VHT_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_VHT_CTRL_MASK 0x000000FF                // CR_BAND1_HND_VHT_CTRL[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_1_CR_BAND1_HND_VHT_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHY_CTRL_2 (0x82000000 + 0x3008)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_BAND1_DIS_OUTER_LOGRST[16] - (RW) [DE] BBP control CR
    CR_BAND1_SEL_OUTER_LOGRST[17] - (RW) [DE] BBP control CR
    CR_BAND1_DIS_OPOST_LOGRST[18] - (RW) [DE] BBP control CR
    CR_BAND1_SEL_OPOST_LOGRST[19] - (RW) [DE] BBP control CR
    CR_BAND1_LTFNUM_CTRL[20]     - (RW) [DE] BBP control CR
    CR_BAND1_RXAIREND_CTRL[21]   - (RW) [DE] BBP control CR
    CR_BAND1_DIS_11N[22]         - (RW) [DE] BBP control CR
    CR_BAND1_MCS_CTRL[23]        - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_MCS_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_MCS_CTRL_MASK 0x00800000                // CR_BAND1_MCS_CTRL[23]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_MCS_CTRL_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_11N_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_11N_MASK 0x00400000                // CR_BAND1_DIS_11N[22]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_11N_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_RXAIREND_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_RXAIREND_CTRL_MASK 0x00200000                // CR_BAND1_RXAIREND_CTRL[21]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_RXAIREND_CTRL_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_LTFNUM_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_LTFNUM_CTRL_MASK 0x00100000                // CR_BAND1_LTFNUM_CTRL[20]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_LTFNUM_CTRL_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_SEL_OPOST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_SEL_OPOST_LOGRST_MASK 0x00080000                // CR_BAND1_SEL_OPOST_LOGRST[19]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_SEL_OPOST_LOGRST_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_OPOST_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_OPOST_LOGRST_MASK 0x00040000                // CR_BAND1_DIS_OPOST_LOGRST[18]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_OPOST_LOGRST_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_SEL_OUTER_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_SEL_OUTER_LOGRST_MASK 0x00020000                // CR_BAND1_SEL_OUTER_LOGRST[17]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_SEL_OUTER_LOGRST_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_OUTER_LOGRST_ADDR WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_OUTER_LOGRST_MASK 0x00010000                // CR_BAND1_DIS_OUTER_LOGRST[16]
#define WF_PHYRX_CTRL_CR_BAND1_PHY_CTRL_2_CR_BAND1_DIS_OUTER_LOGRST_SHFT 16

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS0 (0x82000000 + 0x3010)---

    RO_BAND1_PHYCTRL_STS0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS0_RO_BAND1_PHYCTRL_STS0_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS0_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS0_RO_BAND1_PHYCTRL_STS0_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS0[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS0_RO_BAND1_PHYCTRL_STS0_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS1 (0x82000000 + 0x3014)---

    RO_BAND1_PHYCTRL_STS1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS1_RO_BAND1_PHYCTRL_STS1_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS1_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS1_RO_BAND1_PHYCTRL_STS1_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS1[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS1_RO_BAND1_PHYCTRL_STS1_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS2 (0x82000000 + 0x3018)---

    RO_BAND1_PHYCTRL_STS2[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS2_RO_BAND1_PHYCTRL_STS2_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS2_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS2_RO_BAND1_PHYCTRL_STS2_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS2[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS2_RO_BAND1_PHYCTRL_STS2_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS3 (0x82000000 + 0x301C)---

    RO_BAND1_PHYCTRL_STS3[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS3_RO_BAND1_PHYCTRL_STS3_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS3_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS3_RO_BAND1_PHYCTRL_STS3_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS3[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS3_RO_BAND1_PHYCTRL_STS3_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS4 (0x82000000 + 0x3020)---

    RO_BAND1_PHYCTRL_STS4[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS4_RO_BAND1_PHYCTRL_STS4_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS4_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS4_RO_BAND1_PHYCTRL_STS4_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS4[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS4_RO_BAND1_PHYCTRL_STS4_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS5 (0x82000000 + 0x3024)---

    RO_BAND1_PHYCTRL_STS5[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS5_RO_BAND1_PHYCTRL_STS5_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS5_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS5_RO_BAND1_PHYCTRL_STS5_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS5[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS5_RO_BAND1_PHYCTRL_STS5_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS6 (0x82000000 + 0x3028)---

    RO_BAND1_PHYCTRL_STS6[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS6_RO_BAND1_PHYCTRL_STS6_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS6_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS6_RO_BAND1_PHYCTRL_STS6_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS6[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS6_RO_BAND1_PHYCTRL_STS6_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS7 (0x82000000 + 0x302C)---

    RO_BAND1_PHYCTRL_STS7[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS7_RO_BAND1_PHYCTRL_STS7_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS7_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS7_RO_BAND1_PHYCTRL_STS7_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS7[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS7_RO_BAND1_PHYCTRL_STS7_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS8 (0x82000000 + 0x3030)---

    RO_BAND1_PHYCTRL_STS8[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS8_RO_BAND1_PHYCTRL_STS8_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS8_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS8_RO_BAND1_PHYCTRL_STS8_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS8[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS8_RO_BAND1_PHYCTRL_STS8_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS9 (0x82000000 + 0x3034)---

    RO_BAND1_PHYCTRL_STS9[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS9_RO_BAND1_PHYCTRL_STS9_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS9_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS9_RO_BAND1_PHYCTRL_STS9_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS9[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS9_RO_BAND1_PHYCTRL_STS9_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS_MU (0x82000000 + 0x3038)---

    RO_BAND1_PHYCTRL_STS_MU[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_MU_RO_BAND1_PHYCTRL_STS_MU_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_MU_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_MU_RO_BAND1_PHYCTRL_STS_MU_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS_MU[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_MU_RO_BAND1_PHYCTRL_STS_MU_SHFT 0

/* =====================================================================================

  ---RO_BAND1_PHYCTRL_STS_FSM (0x82000000 + 0x303C)---

    RO_BAND1_PHYCTRL_STS_FSM[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_FSM_RO_BAND1_PHYCTRL_STS_FSM_ADDR WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_FSM_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_FSM_RO_BAND1_PHYCTRL_STS_FSM_MASK 0xFFFFFFFF                // RO_BAND1_PHYCTRL_STS_FSM[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_PHYCTRL_STS_FSM_RO_BAND1_PHYCTRL_STS_FSM_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_DBGCTRL (0x82000000 + 0x3040)---

    CR_BAND1_RXFE_ENAB[0]        - (RW) [DE] BBP control CR
    CR_BAND1_RXFE_ENAB_MANU[1]   - (RW) [DE] BBP control CR
    CR_BAND1_RXTD_ENAB[2]        - (RW) [DE] BBP control CR
    CR_BAND1_RXTD_ENAB_MANU[3]   - (RW) [DE] BBP control CR
    CR_BAND1_FFT_ENAB[4]         - (RW) [DE] BBP control CR
    CR_BAND1_FFT_ENAB_MANU[5]    - (RW) [DE] BBP control CR
    CR_BAND1_OPOST_ENAB[6]       - (RW) [DE] BBP control CR
    CR_BAND1_OPOST_ENAB_MANU[7]  - (RW) [DE] BBP control CR
    CR_BAND1_OUTER_ENAB[8]       - (RW) [DE] BBP control CR
    CR_BAND1_OUTER_ENAB_MANU[9]  - (RW) [DE] BBP control CR
    CR_BAND1_CCKRX_ENAB[10]      - (RW) [DE] BBP control CR
    CR_BAND1_CCKRX_ENAB_MANU[11] - (RW) [DE] BBP control CR
    CR_BAND1_MLD_ENAB[12]        - (RW) [DE] BBP control CR
    CR_BAND1_MLD_ENAB_MANU[13]   - (RW) [DE] BBP control CR
    CR_BAND1_LDPC_ENAB[14]       - (RW) [DE] BBP control CR
    CR_BAND1_LDPC_ENAB_MANU[15]  - (RW) [DE] BBP control CR
    CR_BAND1_TXTD_ENAB[16]       - (RW) [DE] BBP control CR
    CR_BAND1_TXTD_ENAB_MANU[17]  - (RW) [DE] BBP control CR
    RESERVED18[19..18]           - (RO) Reserved bits
    CR_BAND1_FFT_TX_ON_MANU[23..20] - (RW) [DE] BBP control CR
    CR_BAND1_POSTST_FSM_CTRL[24] - (RW) [DE] BBP control CR
    RESERVED25[25]               - (RO) Reserved bits
    CR_BAND1_ROLLBACK_FFT_RST[26] - (RW) [DE] BBP control CR
    CR_BAND1_ROLLBACK_AIR_END[27] - (RW) [DE] BBP control CR
    CR_BAND1_TRIG_SEL[31..28]    - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TRIG_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TRIG_SEL_MASK 0xF0000000                // CR_BAND1_TRIG_SEL[31..28]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TRIG_SEL_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_ROLLBACK_AIR_END_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_ROLLBACK_AIR_END_MASK 0x08000000                // CR_BAND1_ROLLBACK_AIR_END[27]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_ROLLBACK_AIR_END_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_ROLLBACK_FFT_RST_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_ROLLBACK_FFT_RST_MASK 0x04000000                // CR_BAND1_ROLLBACK_FFT_RST[26]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_ROLLBACK_FFT_RST_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_POSTST_FSM_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_POSTST_FSM_CTRL_MASK 0x01000000                // CR_BAND1_POSTST_FSM_CTRL[24]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_POSTST_FSM_CTRL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_TX_ON_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_TX_ON_MANU_MASK 0x00F00000                // CR_BAND1_FFT_TX_ON_MANU[23..20]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_TX_ON_MANU_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TXTD_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TXTD_ENAB_MANU_MASK 0x00020000                // CR_BAND1_TXTD_ENAB_MANU[17]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TXTD_ENAB_MANU_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TXTD_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TXTD_ENAB_MASK 0x00010000                // CR_BAND1_TXTD_ENAB[16]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_TXTD_ENAB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_LDPC_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_LDPC_ENAB_MANU_MASK 0x00008000                // CR_BAND1_LDPC_ENAB_MANU[15]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_LDPC_ENAB_MANU_SHFT 15
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_LDPC_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_LDPC_ENAB_MASK 0x00004000                // CR_BAND1_LDPC_ENAB[14]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_LDPC_ENAB_SHFT 14
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_MLD_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_MLD_ENAB_MANU_MASK 0x00002000                // CR_BAND1_MLD_ENAB_MANU[13]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_MLD_ENAB_MANU_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_MLD_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_MLD_ENAB_MASK 0x00001000                // CR_BAND1_MLD_ENAB[12]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_MLD_ENAB_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_CCKRX_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_CCKRX_ENAB_MANU_MASK 0x00000800                // CR_BAND1_CCKRX_ENAB_MANU[11]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_CCKRX_ENAB_MANU_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_CCKRX_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_CCKRX_ENAB_MASK 0x00000400                // CR_BAND1_CCKRX_ENAB[10]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_CCKRX_ENAB_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OUTER_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OUTER_ENAB_MANU_MASK 0x00000200                // CR_BAND1_OUTER_ENAB_MANU[9]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OUTER_ENAB_MANU_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OUTER_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OUTER_ENAB_MASK 0x00000100                // CR_BAND1_OUTER_ENAB[8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OUTER_ENAB_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OPOST_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OPOST_ENAB_MANU_MASK 0x00000080                // CR_BAND1_OPOST_ENAB_MANU[7]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OPOST_ENAB_MANU_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OPOST_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OPOST_ENAB_MASK 0x00000040                // CR_BAND1_OPOST_ENAB[6]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_OPOST_ENAB_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_ENAB_MANU_MASK 0x00000020                // CR_BAND1_FFT_ENAB_MANU[5]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_ENAB_MANU_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_ENAB_MASK 0x00000010                // CR_BAND1_FFT_ENAB[4]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_FFT_ENAB_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXTD_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXTD_ENAB_MANU_MASK 0x00000008                // CR_BAND1_RXTD_ENAB_MANU[3]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXTD_ENAB_MANU_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXTD_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXTD_ENAB_MASK 0x00000004                // CR_BAND1_RXTD_ENAB[2]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXTD_ENAB_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXFE_ENAB_MANU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXFE_ENAB_MANU_MASK 0x00000002                // CR_BAND1_RXFE_ENAB_MANU[1]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXFE_ENAB_MANU_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXFE_ENAB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXFE_ENAB_MASK 0x00000001                // CR_BAND1_RXFE_ENAB[0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_DBGCTRL_CR_BAND1_RXFE_ENAB_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_POPCTRL (0x82000000 + 0x3044)---

    CR_BAND1_POP_RX_LEN[23..0]   - (RW) [DE] BBP control CR
    RESERVED24[30..24]           - (RO) Reserved bits
    CR_BAND1_POP_FILTER[31]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_CR_BAND1_POP_FILTER_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_CR_BAND1_POP_FILTER_MASK 0x80000000                // CR_BAND1_POP_FILTER[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_CR_BAND1_POP_FILTER_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_CR_BAND1_POP_RX_LEN_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_CR_BAND1_POP_RX_LEN_MASK 0x00FFFFFF                // CR_BAND1_POP_RX_LEN[23..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_POPCTRL_CR_BAND1_POP_RX_LEN_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_RXTD_ENAB (0x82000000 + 0x3048)---

    CR_BAND1_DLY_FALL_RXTD[7..0] - (RW) [DE] BBP control CR
    CR_BAND1_DLY_RISE_RXTD[15..8] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_CR_BAND1_DLY_RISE_RXTD_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_CR_BAND1_DLY_RISE_RXTD_MASK 0x0000FF00                // CR_BAND1_DLY_RISE_RXTD[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_CR_BAND1_DLY_RISE_RXTD_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_CR_BAND1_DLY_FALL_RXTD_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_CR_BAND1_DLY_FALL_RXTD_MASK 0x000000FF                // CR_BAND1_DLY_FALL_RXTD[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RXTD_ENAB_CR_BAND1_DLY_FALL_RXTD_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_RATE_CTRL (0x82000000 + 0x304C)---

    CR_BAND1_VHT_SPRT_NSS_CHK[7..0] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_SPRT_NDP_CHK[15..8] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_NDP_BYP_SIGB[16] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_NDP_BYP_SNGU[17] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_NDP_BYP_ZLEN[18] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_SYM_CNT_MODE[19] - (RW) [DE] BBP control CR
    CR_BAND1_HT_SPRT_NSS_CHK[23..20] - (RW) [DE] BBP control CR
    CR_BAND1_HT_SPRT_NDP_CHK[27..24] - (RW) [DE] BBP control CR
    CR_BAND1_HT_NDP_BYP_HSIG[28] - (RW) [DE] BBP control CR
    CR_BAND1_HT_NDP_BYP_ZLEN[29] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_SKIP_ANT_CHK[30] - (RW) [DE] BBP control CR
    CR_BAND1_HT_SKIP_ANT_CHK[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SKIP_ANT_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SKIP_ANT_CHK_MASK 0x80000000                // CR_BAND1_HT_SKIP_ANT_CHK[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SKIP_ANT_CHK_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SKIP_ANT_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SKIP_ANT_CHK_MASK 0x40000000                // CR_BAND1_VHT_SKIP_ANT_CHK[30]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SKIP_ANT_CHK_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_NDP_BYP_ZLEN_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_NDP_BYP_ZLEN_MASK 0x20000000                // CR_BAND1_HT_NDP_BYP_ZLEN[29]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_NDP_BYP_ZLEN_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_NDP_BYP_HSIG_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_NDP_BYP_HSIG_MASK 0x10000000                // CR_BAND1_HT_NDP_BYP_HSIG[28]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_NDP_BYP_HSIG_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SPRT_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SPRT_NDP_CHK_MASK 0x0F000000                // CR_BAND1_HT_SPRT_NDP_CHK[27..24]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SPRT_NDP_CHK_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SPRT_NSS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SPRT_NSS_CHK_MASK 0x00F00000                // CR_BAND1_HT_SPRT_NSS_CHK[23..20]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_HT_SPRT_NSS_CHK_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SYM_CNT_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SYM_CNT_MODE_MASK 0x00080000                // CR_BAND1_VHT_SYM_CNT_MODE[19]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SYM_CNT_MODE_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_ZLEN_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_ZLEN_MASK 0x00040000                // CR_BAND1_VHT_NDP_BYP_ZLEN[18]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_ZLEN_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_SNGU_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_SNGU_MASK 0x00020000                // CR_BAND1_VHT_NDP_BYP_SNGU[17]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_SNGU_SHFT 17
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_SIGB_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_SIGB_MASK 0x00010000                // CR_BAND1_VHT_NDP_BYP_SIGB[16]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_NDP_BYP_SIGB_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SPRT_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SPRT_NDP_CHK_MASK 0x0000FF00                // CR_BAND1_VHT_SPRT_NDP_CHK[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SPRT_NDP_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SPRT_NSS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SPRT_NSS_CHK_MASK 0x000000FF                // CR_BAND1_VHT_SPRT_NSS_CHK[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_RATE_CTRL_CR_BAND1_VHT_SPRT_NSS_CHK_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_GIDTAB (0x82000000 + 0x3050)---

    B1_CM_GID_TAB_UPD_ALL[0]     - (RW) [DE] BBP control CR
    B1_CM_GID_TAB_CLR_ALL[1]     - (RW) [DE] BBP control CR
    RESERVED2[15..2]             - (RO) Reserved bits
    CR_BAND1_GID_TAB_TEST_GID[21..16] - (RW) [DE] BBP control CR
    RESERVED22[23..22]           - (RO) Reserved bits
    B1_CM_GID_TAB_TEST_UPD[24]   - (RW) [DE] BBP control CR
    RESERVED25[30..25]           - (RO) Reserved bits
    CR_BAND1_GID_TAB_TEST_MODE[31] - (RW) 0x4160

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_CR_BAND1_GID_TAB_TEST_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_CR_BAND1_GID_TAB_TEST_MODE_MASK 0x80000000                // CR_BAND1_GID_TAB_TEST_MODE[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_CR_BAND1_GID_TAB_TEST_MODE_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_TEST_UPD_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_TEST_UPD_MASK 0x01000000                // B1_CM_GID_TAB_TEST_UPD[24]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_TEST_UPD_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_CR_BAND1_GID_TAB_TEST_GID_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_CR_BAND1_GID_TAB_TEST_GID_MASK 0x003F0000                // CR_BAND1_GID_TAB_TEST_GID[21..16]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_CR_BAND1_GID_TAB_TEST_GID_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_CLR_ALL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_CLR_ALL_MASK 0x00000002                // B1_CM_GID_TAB_CLR_ALL[1]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_CLR_ALL_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_UPD_ALL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_UPD_ALL_MASK 0x00000001                // B1_CM_GID_TAB_UPD_ALL[0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_GIDTAB_B1_CM_GID_TAB_UPD_ALL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_GID_TAB_VLD_0 (0x82000000 + 0x3054)---

    RESERVED0[0]                 - (RO) Reserved bits
    CR_BAND1_GID_TAB_VLD_0[31..1] - (RW) 0x4164

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_0_CR_BAND1_GID_TAB_VLD_0_ADDR WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_0_CR_BAND1_GID_TAB_VLD_0_MASK 0xFFFFFFFE                // CR_BAND1_GID_TAB_VLD_0[31..1]
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_0_CR_BAND1_GID_TAB_VLD_0_SHFT 1

/* =====================================================================================

  ---CR_BAND1_GID_TAB_VLD_1 (0x82000000 + 0x3058)---

    CR_BAND1_GID_TAB_VLD_1[30..0] - (RW) 0x4168
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_1_CR_BAND1_GID_TAB_VLD_1_ADDR WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_1_CR_BAND1_GID_TAB_VLD_1_MASK 0x7FFFFFFF                // CR_BAND1_GID_TAB_VLD_1[30..0]
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_VLD_1_CR_BAND1_GID_TAB_VLD_1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_GID_TAB_POS_0 (0x82000000 + 0x305C)---

    RESERVED0[1..0]              - (RO) Reserved bits
    CR_BAND1_GID_TAB_POS_0[31..2] - (RW) 0x416C

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_0_CR_BAND1_GID_TAB_POS_0_ADDR WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_0_CR_BAND1_GID_TAB_POS_0_MASK 0xFFFFFFFC                // CR_BAND1_GID_TAB_POS_0[31..2]
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_0_CR_BAND1_GID_TAB_POS_0_SHFT 2

/* =====================================================================================

  ---CR_BAND1_GID_TAB_POS_1 (0x82000000 + 0x3060)---

    CR_BAND1_GID_TAB_POS_1[31..0] - (RW) 0x4170

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_1_CR_BAND1_GID_TAB_POS_1_ADDR WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_1_CR_BAND1_GID_TAB_POS_1_MASK 0xFFFFFFFF                // CR_BAND1_GID_TAB_POS_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_1_CR_BAND1_GID_TAB_POS_1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_GID_TAB_POS_2 (0x82000000 + 0x3064)---

    CR_BAND1_GID_TAB_POS_2[31..0] - (RW) 0x4174

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_2_CR_BAND1_GID_TAB_POS_2_ADDR WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_2_CR_BAND1_GID_TAB_POS_2_MASK 0xFFFFFFFF                // CR_BAND1_GID_TAB_POS_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_2_CR_BAND1_GID_TAB_POS_2_SHFT 0

/* =====================================================================================

  ---CR_BAND1_GID_TAB_POS_3 (0x82000000 + 0x3068)---

    CR_BAND1_GID_TAB_POS_3[29..0] - (RW) 0x4178
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_3_CR_BAND1_GID_TAB_POS_3_ADDR WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_3_CR_BAND1_GID_TAB_POS_3_MASK 0x3FFFFFFF                // CR_BAND1_GID_TAB_POS_3[29..0]
#define WF_PHYRX_CTRL_CR_BAND1_GID_TAB_POS_3_CR_BAND1_GID_TAB_POS_3_SHFT 0

/* =====================================================================================

  ---RO_BAND1_GIDTAB_STATUS (0x82000000 + 0x306C)---

    RO_BAND1_GID_TAB_STATUS[31..0] - (RO) 0x4184

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_GIDTAB_STATUS_RO_BAND1_GID_TAB_STATUS_ADDR WF_PHYRX_CTRL_RO_BAND1_GIDTAB_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_GIDTAB_STATUS_RO_BAND1_GID_TAB_STATUS_MASK 0xFFFFFFFF                // RO_BAND1_GID_TAB_STATUS[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_GIDTAB_STATUS_RO_BAND1_GID_TAB_STATUS_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_BF_CTRL (0x82000000 + 0x3080)---

    CR_BAND1_IBF_DIS_LNA_ULG[0]  - (RW) [DE] BBP control CR
    CR_BAND1_IBF_DIS_LNA_LG[1]   - (RW) [DE] BBP control CR
    CR_BAND1_IBF_DIS_LNA_MG[2]   - (RW) [DE] BBP control CR
    CR_BAND1_IBF_DIS_LNA_HG[3]   - (RW) [DE] BBP control CR
    CR_BAND1_IBF_DIS_LNA_DIFF[4] - (RW) [DE] BBP control CR
    CR_BAND1_IBF_SM_BIT_BYPASS[5] - (RW) [DE] BBP control CR
    CR_BAND1_IBF_BF_BIT_BYPASS[6] - (RW) [DE] BBP control CR
    CR_BAND1_IBF_DONE_POLLING_DIS[7] - (RW) [DE] BBP control CR
    CR_BAND1_BFEE_SOUND_N_BYPASS[8] - (RW) [DE] BBP control CR
    CR_BAND1_IBF_DIS_LNA_UHG[9]  - (RW) [DE] BBP control CR
    CR_BAND1_IBF_AGC_QUAL_RX_ON_REV[10] - (RW) [DE] BBP control CR
    RESERVED11[11]               - (RO) Reserved bits
    CR_BAND1_HT_NDP_BYP_BFEE_SOUND[12] - (RW) [DE] BBP control CR
    RESERVED13[29..13]           - (RO) Reserved bits
    CR_BAND1_ROLLBACK_FFT_NBID[30] - (RW) [DE] BBP control CR
    CR_BAND1_ROLLBACK_FFT_STOP[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_ROLLBACK_FFT_STOP_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_ROLLBACK_FFT_STOP_MASK 0x80000000                // CR_BAND1_ROLLBACK_FFT_STOP[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_ROLLBACK_FFT_STOP_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_ROLLBACK_FFT_NBID_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_ROLLBACK_FFT_NBID_MASK 0x40000000                // CR_BAND1_ROLLBACK_FFT_NBID[30]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_ROLLBACK_FFT_NBID_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_HT_NDP_BYP_BFEE_SOUND_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_HT_NDP_BYP_BFEE_SOUND_MASK 0x00001000                // CR_BAND1_HT_NDP_BYP_BFEE_SOUND[12]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_HT_NDP_BYP_BFEE_SOUND_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_AGC_QUAL_RX_ON_REV_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_AGC_QUAL_RX_ON_REV_MASK 0x00000400                // CR_BAND1_IBF_AGC_QUAL_RX_ON_REV[10]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_AGC_QUAL_RX_ON_REV_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_UHG_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_UHG_MASK 0x00000200                // CR_BAND1_IBF_DIS_LNA_UHG[9]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_UHG_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_BFEE_SOUND_N_BYPASS_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_BFEE_SOUND_N_BYPASS_MASK 0x00000100                // CR_BAND1_BFEE_SOUND_N_BYPASS[8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_BFEE_SOUND_N_BYPASS_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DONE_POLLING_DIS_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DONE_POLLING_DIS_MASK 0x00000080                // CR_BAND1_IBF_DONE_POLLING_DIS[7]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DONE_POLLING_DIS_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_BF_BIT_BYPASS_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_BF_BIT_BYPASS_MASK 0x00000040                // CR_BAND1_IBF_BF_BIT_BYPASS[6]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_BF_BIT_BYPASS_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_SM_BIT_BYPASS_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_SM_BIT_BYPASS_MASK 0x00000020                // CR_BAND1_IBF_SM_BIT_BYPASS[5]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_SM_BIT_BYPASS_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_DIFF_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_DIFF_MASK 0x00000010                // CR_BAND1_IBF_DIS_LNA_DIFF[4]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_DIFF_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_HG_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_HG_MASK 0x00000008                // CR_BAND1_IBF_DIS_LNA_HG[3]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_HG_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_MG_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_MG_MASK 0x00000004                // CR_BAND1_IBF_DIS_LNA_MG[2]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_MG_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_LG_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_LG_MASK 0x00000002                // CR_BAND1_IBF_DIS_LNA_LG[1]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_LG_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_ULG_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_ULG_MASK 0x00000001                // CR_BAND1_IBF_DIS_LNA_ULG[0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_BF_CTRL_CR_BAND1_IBF_DIS_LNA_ULG_SHFT 0

/* =====================================================================================

  ---CR_BAND1_SIG_DEC_CTRL (0x82000000 + 0x3090)---

    CR_BAND1_LGSIG_LEN_CHK[0]    - (RW) 1: Enable, 0: disable
    CR_BAND1_LGSIG_NDP_CHK[1]    - (RW) 1: Enable, 0: disable
    CR_BAND1_LGSIG_R4_CHK[2]     - (RW) [DE] BBP control CR
    CR_BAND1_LGSIG_PARITY_CHK[3] - (RW) [DE] BBP control CR
    CR_BAND1_HTSIG_LEN_CHK[4]    - (RW) 1: Enable, 0: disable
    CR_BAND1_HTSIG_NDP_CHK[5]    - (RW) 1: Enable, 0: disable
    CR_BAND1_HTSIG_CBW_CHK[6]    - (RW) 1: Enable, 0: disable
    CR_BAND1_HTSIG_RATE_CHK[7]   - (RW) 1: Enable, 0: disable
    CR_BAND1_VHTSIGA_LEN_CHK[8]  - (RW) 1: Enable, 0: disable
    CR_BAND1_VHTSIGA_NDP_CHK[9]  - (RW) 1: Enable, 0: disable
    CR_BAND1_VHTSIGA_CBW_CHK[10] - (RW) 1: Enable, 0: disable
    CR_BAND1_VHTSIGA_DBW_CHK[11] - (RW) 1: Enable, 0: disable
    CR_BAND1_VHTSIGA_RATE_CHK[12] - (RW) 1: Enable, 0: disable
    CR_BAND1_VHTSIGB_CHK[15..13] - (RW) Bit[15] 1: enable RX_VLD_ALL_STS check; 0: Bypass
                                     Bit[14] 1: enable SIGB check in MU; 0: Disable
                                     Bit[13] 1: enable SIGB check in SU; 0: Disable
    CR_BAND1_RXVEC_BW_RPT_TYPE[17..16] - (RW) 00: RX_BW, which is updated by BWD & SIGNAL Field
                                     01: POST BWD Results
                                     10: RXTD CBW2DBW Ratio
                                     11: Force CBW to BW20
    CR_BAND1_DIS_RXTD_FFT_RST[18] - (RW) 1: Disable FFT Reset from RXTD
                                     0: Enable
    CR_BAND1_HT_SKIP_STBC_CHK[19] - (RW) 1: Enable, 0: Disable
    CR_BAND1_HTSIG_STBC_CHK[20]  - (RW) 1: Enable, 0: Disable
    CR_BAND1_HT_NDP_BYP_STBC[21] - (RW) 1: Enable, 0: Disable
    CR_BAND1_HT_SKIP_MCS_CHK[22] - (RW) 1: Enable, 1: Disable
    CR_BAND1_HTSIG_NLTF_CHK[23]  - (RW) [DE] BBP control CR
    CR_BAND1_VHT_SKIP_STBC_CHK[24] - (RW) 1: Enable, 0: Disable
    CR_BAND1_VHT_SKIP_MCS_CHK[25] - (RW) [DE] BBP control CR
    CR_BAND1_VHT_DIS_MU_PPDU[26] - (RW) 1: Disable MU_PPDU RX
                                     0: Allow MU PPDU RX
    CR_BAND1_VHT_RSVD[27]        - (RW) [DE] BBP control CR
    CR_BAND1_VHT_IEEE_MCS_ONLY[28] - (RW) [DE] BBP control CR
    CR_BAND1_CCK_SKIP_SHORT_ERR[29] - (RW) [DE] BBP control CR
    CR_BAND1_DISABLE_NESS_UNSPRT[30] - (RW) Reserved CR
    CR_BAND1_DISABLE_LDPC_UNSPRT[31] - (RW) Reserved CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DISABLE_LDPC_UNSPRT_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DISABLE_LDPC_UNSPRT_MASK 0x80000000                // CR_BAND1_DISABLE_LDPC_UNSPRT[31]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DISABLE_LDPC_UNSPRT_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DISABLE_NESS_UNSPRT_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DISABLE_NESS_UNSPRT_MASK 0x40000000                // CR_BAND1_DISABLE_NESS_UNSPRT[30]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DISABLE_NESS_UNSPRT_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_CCK_SKIP_SHORT_ERR_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_CCK_SKIP_SHORT_ERR_MASK 0x20000000                // CR_BAND1_CCK_SKIP_SHORT_ERR[29]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_CCK_SKIP_SHORT_ERR_SHFT 29
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_IEEE_MCS_ONLY_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_IEEE_MCS_ONLY_MASK 0x10000000                // CR_BAND1_VHT_IEEE_MCS_ONLY[28]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_IEEE_MCS_ONLY_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_RSVD_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_RSVD_MASK 0x08000000                // CR_BAND1_VHT_RSVD[27]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_RSVD_SHFT 27
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_DIS_MU_PPDU_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_DIS_MU_PPDU_MASK 0x04000000                // CR_BAND1_VHT_DIS_MU_PPDU[26]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_DIS_MU_PPDU_SHFT 26
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_SKIP_MCS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_SKIP_MCS_CHK_MASK 0x02000000                // CR_BAND1_VHT_SKIP_MCS_CHK[25]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_SKIP_MCS_CHK_SHFT 25
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_SKIP_STBC_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_SKIP_STBC_CHK_MASK 0x01000000                // CR_BAND1_VHT_SKIP_STBC_CHK[24]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHT_SKIP_STBC_CHK_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_NLTF_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_NLTF_CHK_MASK 0x00800000                // CR_BAND1_HTSIG_NLTF_CHK[23]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_NLTF_CHK_SHFT 23
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_SKIP_MCS_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_SKIP_MCS_CHK_MASK 0x00400000                // CR_BAND1_HT_SKIP_MCS_CHK[22]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_SKIP_MCS_CHK_SHFT 22
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_NDP_BYP_STBC_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_NDP_BYP_STBC_MASK 0x00200000                // CR_BAND1_HT_NDP_BYP_STBC[21]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_NDP_BYP_STBC_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_STBC_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_STBC_CHK_MASK 0x00100000                // CR_BAND1_HTSIG_STBC_CHK[20]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_STBC_CHK_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_SKIP_STBC_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_SKIP_STBC_CHK_MASK 0x00080000                // CR_BAND1_HT_SKIP_STBC_CHK[19]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HT_SKIP_STBC_CHK_SHFT 19
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DIS_RXTD_FFT_RST_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DIS_RXTD_FFT_RST_MASK 0x00040000                // CR_BAND1_DIS_RXTD_FFT_RST[18]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_DIS_RXTD_FFT_RST_SHFT 18
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_RXVEC_BW_RPT_TYPE_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_RXVEC_BW_RPT_TYPE_MASK 0x00030000                // CR_BAND1_RXVEC_BW_RPT_TYPE[17..16]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_RXVEC_BW_RPT_TYPE_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGB_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGB_CHK_MASK 0x0000E000                // CR_BAND1_VHTSIGB_CHK[15..13]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGB_CHK_SHFT 13
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_RATE_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_RATE_CHK_MASK 0x00001000                // CR_BAND1_VHTSIGA_RATE_CHK[12]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_RATE_CHK_SHFT 12
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_DBW_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_DBW_CHK_MASK 0x00000800                // CR_BAND1_VHTSIGA_DBW_CHK[11]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_DBW_CHK_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_CBW_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_CBW_CHK_MASK 0x00000400                // CR_BAND1_VHTSIGA_CBW_CHK[10]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_CBW_CHK_SHFT 10
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_NDP_CHK_MASK 0x00000200                // CR_BAND1_VHTSIGA_NDP_CHK[9]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_NDP_CHK_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_LEN_CHK_MASK 0x00000100                // CR_BAND1_VHTSIGA_LEN_CHK[8]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_VHTSIGA_LEN_CHK_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_RATE_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_RATE_CHK_MASK 0x00000080                // CR_BAND1_HTSIG_RATE_CHK[7]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_RATE_CHK_SHFT 7
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_CBW_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_CBW_CHK_MASK 0x00000040                // CR_BAND1_HTSIG_CBW_CHK[6]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_CBW_CHK_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_NDP_CHK_MASK 0x00000020                // CR_BAND1_HTSIG_NDP_CHK[5]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_NDP_CHK_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_LEN_CHK_MASK 0x00000010                // CR_BAND1_HTSIG_LEN_CHK[4]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_HTSIG_LEN_CHK_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_PARITY_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_PARITY_CHK_MASK 0x00000008                // CR_BAND1_LGSIG_PARITY_CHK[3]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_PARITY_CHK_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_R4_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_R4_CHK_MASK 0x00000004                // CR_BAND1_LGSIG_R4_CHK[2]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_R4_CHK_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_NDP_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_NDP_CHK_MASK 0x00000002                // CR_BAND1_LGSIG_NDP_CHK[1]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_NDP_CHK_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_LEN_CHK_ADDR WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_LEN_CHK_MASK 0x00000001                // CR_BAND1_LGSIG_LEN_CHK[0]
#define WF_PHYRX_CTRL_CR_BAND1_SIG_DEC_CTRL_CR_BAND1_LGSIG_LEN_CHK_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_FSM (0x82000000 + 0x3094)---

    CR_BAND1_POSTST_TIMEOUT[7..0] - (RW) [DE] BBP control CR
    CR_BAND1_PREST_TIMEOUT[15..8] - (RW) [DE] BBP control CR
    CR_BAND1_BEAMFORM_TIMEOUT[31..16] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_BEAMFORM_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_BEAMFORM_TIMEOUT_MASK 0xFFFF0000                // CR_BAND1_BEAMFORM_TIMEOUT[31..16]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_BEAMFORM_TIMEOUT_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_PREST_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_PREST_TIMEOUT_MASK 0x0000FF00                // CR_BAND1_PREST_TIMEOUT[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_PREST_TIMEOUT_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_POSTST_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_POSTST_TIMEOUT_MASK 0x000000FF                // CR_BAND1_POSTST_TIMEOUT[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_FSM_CR_BAND1_POSTST_TIMEOUT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_AIRST (0x82000000 + 0x3098)---

    CR_BAND1_AIRST_CCKRX_TIMEOUT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[19..16]           - (RO) Reserved bits
    CR_BAND1_CCKRX_TIMER_ADVANCE[27..20] - (RW) [DE] BBP control CR
    CR_BAND1_CCKRX_TIMER_MODE[28] - (RW) [DE] BBP control CR
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_CCKRX_TIMER_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_CCKRX_TIMER_MODE_MASK 0x10000000                // CR_BAND1_CCKRX_TIMER_MODE[28]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_CCKRX_TIMER_MODE_SHFT 28
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_CCKRX_TIMER_ADVANCE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_CCKRX_TIMER_ADVANCE_MASK 0x0FF00000                // CR_BAND1_CCKRX_TIMER_ADVANCE[27..20]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_CCKRX_TIMER_ADVANCE_SHFT 20
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_AIRST_CCKRX_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_AIRST_CCKRX_TIMEOUT_MASK 0x0000FFFF                // CR_BAND1_AIRST_CCKRX_TIMEOUT[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_AIRST_CR_BAND1_AIRST_CCKRX_TIMEOUT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_ERR (0x82000000 + 0x309C)---

    CR_BAND1_ABERR_MASK[15..0]   - (RW) [DE] BBP control CR
    CR_BAND1_POSTST_WEND_TIMEOUT[23..16] - (RW) [DE] BBP control CR
    CR_BAND1_BBRX_AIREND_TIMEOUT[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_BBRX_AIREND_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_BBRX_AIREND_TIMEOUT_MASK 0xFF000000                // CR_BAND1_BBRX_AIREND_TIMEOUT[31..24]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_BBRX_AIREND_TIMEOUT_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_POSTST_WEND_TIMEOUT_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_POSTST_WEND_TIMEOUT_MASK 0x00FF0000                // CR_BAND1_POSTST_WEND_TIMEOUT[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_POSTST_WEND_TIMEOUT_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_ABERR_MASK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_ABERR_MASK_MASK 0x0000FFFF                // CR_BAND1_ABERR_MASK[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_ERR_CR_BAND1_ABERR_MASK_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYCTRL_STSCNTR (0x82000000 + 0x30A0)---

    CR_BAND1_STSCNTR_SEL_RX_0[4..0] - (RW)  xxx
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_BAND1_STSCNTR_SEL_RX_1[12..8] - (RW)  xxx
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_BAND1_STSCNTR_SEL_MU_0[17..16] - (RW)  xxx
    RESERVED18[23..18]           - (RO) Reserved bits
    CR_BAND1_STSCNTR_SEL_MU_1[25..24] - (RW) [DE] BBP Counters
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_MU_1_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_MU_1_MASK 0x03000000                // CR_BAND1_STSCNTR_SEL_MU_1[25..24]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_MU_1_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_MU_0_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_MU_0_MASK 0x00030000                // CR_BAND1_STSCNTR_SEL_MU_0[17..16]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_MU_0_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_RX_1_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_RX_1_MASK 0x00001F00                // CR_BAND1_STSCNTR_SEL_RX_1[12..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_RX_1_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_RX_0_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_RX_0_MASK 0x0000001F                // CR_BAND1_STSCNTR_SEL_RX_0[4..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYCTRL_STSCNTR_CR_BAND1_STSCNTR_SEL_RX_0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_CTRL_0 (0x82000000 + 0x3900)---

    CR_BAND1_BBRX_ENA[7..0]      - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND1_BBRX_OFF[15..8]     - (RW) [DE] BBP PHYINTF RX control CR
    RESERVED16[29..16]           - (RO) Reserved bits
    CR_BAND1_DIS_ST_ERR[30]      - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND1_DIS_EVM[31]         - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_DIS_EVM_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_DIS_EVM_MASK 0x80000000                // CR_BAND1_DIS_EVM[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_DIS_EVM_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_DIS_ST_ERR_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_DIS_ST_ERR_MASK 0x40000000                // CR_BAND1_DIS_ST_ERR[30]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_DIS_ST_ERR_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_BBRX_OFF_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_BBRX_OFF_MASK 0x0000FF00                // CR_BAND1_BBRX_OFF[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_BBRX_OFF_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_BBRX_ENA_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_BBRX_ENA_MASK 0x000000FF                // CR_BAND1_BBRX_ENA[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_0_CR_BAND1_BBRX_ENA_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_CTRL_1 (0x82000000 + 0x3904)---

    CR_BAND1_IPI_EN_CTRL[2..0]   - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND1_RPI_EN_CTRL[5..3]   - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND1_RDD_EN_CTRL[8..6]   - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND1_STSCNT_EN_CTRL[11..9] - (RW) [DE] BBP PHYINTF RX control CR
    RESERVED12[29..12]           - (RO) Reserved bits
    CR_BAND1_PHYINTF_MDRDY_MASK[31..30] - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_PHYINTF_MDRDY_MASK_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_PHYINTF_MDRDY_MASK_MASK 0xC0000000                // CR_BAND1_PHYINTF_MDRDY_MASK[31..30]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_PHYINTF_MDRDY_MASK_SHFT 30
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_STSCNT_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_STSCNT_EN_CTRL_MASK 0x00000E00                // CR_BAND1_STSCNT_EN_CTRL[11..9]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_STSCNT_EN_CTRL_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_RDD_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_RDD_EN_CTRL_MASK 0x000001C0                // CR_BAND1_RDD_EN_CTRL[8..6]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_RDD_EN_CTRL_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_RPI_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_RPI_EN_CTRL_MASK 0x00000038                // CR_BAND1_RPI_EN_CTRL[5..3]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_RPI_EN_CTRL_SHFT 3
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_IPI_EN_CTRL_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_IPI_EN_CTRL_MASK 0x00000007                // CR_BAND1_IPI_EN_CTRL[2..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_1_CR_BAND1_IPI_EN_CTRL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_CTRL_2 (0x82000000 + 0x3910)---

    CR_BAND1_RXAFT_SEL_0[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_2_CR_BAND1_RXAFT_SEL_0_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_2_CR_BAND1_RXAFT_SEL_0_MASK 0xFFFFFFFF                // CR_BAND1_RXAFT_SEL_0[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_2_CR_BAND1_RXAFT_SEL_0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_CTRL_3 (0x82000000 + 0x3914)---

    CR_BAND1_RXAFT_SEL_1[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_3_CR_BAND1_RXAFT_SEL_1_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_3_CR_BAND1_RXAFT_SEL_1_MASK 0xFFFFFFFF                // CR_BAND1_RXAFT_SEL_1[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_3_CR_BAND1_RXAFT_SEL_1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_CTRL_4 (0x82000000 + 0x3918)---

    CR_BAND1_RXAFT_SEL_2[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_4_CR_BAND1_RXAFT_SEL_2_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_4_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_4_CR_BAND1_RXAFT_SEL_2_MASK 0xFFFFFFFF                // CR_BAND1_RXAFT_SEL_2[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_4_CR_BAND1_RXAFT_SEL_2_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_CTRL_5 (0x82000000 + 0x391C)---

    CR_BAND1_RXAFT_SEL_3[31..0]  - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_5_CR_BAND1_RXAFT_SEL_3_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_5_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_5_CR_BAND1_RXAFT_SEL_3_MASK 0xFFFFFFFF                // CR_BAND1_RXAFT_SEL_3[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_CTRL_5_CR_BAND1_RXAFT_SEL_3_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYINTF_RX_MANUAL_MODE_0 (0x82000000 + 0x3928)---

    RESERVED0[29..0]             - (RO) Reserved bits
    CR_BAND1_PHYINTF_RX_MANUAL_ON[30] - (RW) [DE] BBP PHYINTF RX control CR
    CR_BAND1_PHYINTF_RX_MANUAL_MODE[31] - (RW) [DE] BBP PHYINTF RX control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_CR_BAND1_PHYINTF_RX_MANUAL_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_CR_BAND1_PHYINTF_RX_MANUAL_MODE_MASK 0x80000000                // CR_BAND1_PHYINTF_RX_MANUAL_MODE[31]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_CR_BAND1_PHYINTF_RX_MANUAL_MODE_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_CR_BAND1_PHYINTF_RX_MANUAL_ON_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_CR_BAND1_PHYINTF_RX_MANUAL_ON_MASK 0x40000000                // CR_BAND1_PHYINTF_RX_MANUAL_ON[30]
#define WF_PHYRX_CTRL_CR_BAND1_PHYINTF_RX_MANUAL_MODE_0_CR_BAND1_PHYINTF_RX_MANUAL_ON_SHFT 30

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV_GAP (0x82000000 + 0x3A3C)---

    CR_BAND1_PHYMUX_MAN_TXV_GAP_0[15..0] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_MAN_TXV_GAP_1[30..16] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_MAN_TXV_GAP_AON[31] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_AON_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_AON_MASK 0x80000000                // CR_BAND1_PHYMUX_MAN_TXV_GAP_AON[31]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_AON_SHFT 31
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_1_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_1_MASK 0x7FFF0000                // CR_BAND1_PHYMUX_MAN_TXV_GAP_1[30..16]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_1_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_0_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_0_MASK 0x0000FFFF                // CR_BAND1_PHYMUX_MAN_TXV_GAP_0[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV_GAP_CR_BAND1_PHYMUX_MAN_TXV_GAP_0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TX_MODE_0 (0x82000000 + 0x3A40)---

    CR_BAND1_PHYMUX_MANUAL_GAP[13..0] - (RW) [DE] BBP control CR
    RESERVED14[23..14]           - (RO) Reserved bits
    CR_BAND1_PHYMUX_TXV_MANUAL_MODE[24] - (RW) [DE] BBP control CR
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_CR_BAND1_PHYMUX_TXV_MANUAL_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_CR_BAND1_PHYMUX_TXV_MANUAL_MODE_MASK 0x01000000                // CR_BAND1_PHYMUX_TXV_MANUAL_MODE[24]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_CR_BAND1_PHYMUX_TXV_MANUAL_MODE_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_CR_BAND1_PHYMUX_MANUAL_GAP_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_CR_BAND1_PHYMUX_MANUAL_GAP_MASK 0x00003FFF                // CR_BAND1_PHYMUX_MANUAL_GAP[13..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_0_CR_BAND1_PHYMUX_MANUAL_GAP_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV0 (0x82000000 + 0x3A44)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V0[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV0_CR_BAND1_PHYMUX_TXV_MANUAL_V0_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV0_CR_BAND1_PHYMUX_TXV_MANUAL_V0_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V0[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV0_CR_BAND1_PHYMUX_TXV_MANUAL_V0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV1 (0x82000000 + 0x3A48)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV1_CR_BAND1_PHYMUX_TXV_MANUAL_V1_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV1_CR_BAND1_PHYMUX_TXV_MANUAL_V1_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V1[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV1_CR_BAND1_PHYMUX_TXV_MANUAL_V1_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV2 (0x82000000 + 0x3A4C)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V2[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV2_CR_BAND1_PHYMUX_TXV_MANUAL_V2_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV2_CR_BAND1_PHYMUX_TXV_MANUAL_V2_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V2[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV2_CR_BAND1_PHYMUX_TXV_MANUAL_V2_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV3 (0x82000000 + 0x3A50)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V3[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV3_CR_BAND1_PHYMUX_TXV_MANUAL_V3_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV3_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV3_CR_BAND1_PHYMUX_TXV_MANUAL_V3_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V3[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV3_CR_BAND1_PHYMUX_TXV_MANUAL_V3_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV4 (0x82000000 + 0x3A54)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V4[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV4_CR_BAND1_PHYMUX_TXV_MANUAL_V4_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV4_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV4_CR_BAND1_PHYMUX_TXV_MANUAL_V4_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V4[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV4_CR_BAND1_PHYMUX_TXV_MANUAL_V4_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV5 (0x82000000 + 0x3A58)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V5[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV5_CR_BAND1_PHYMUX_TXV_MANUAL_V5_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV5_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV5_CR_BAND1_PHYMUX_TXV_MANUAL_V5_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V5[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV5_CR_BAND1_PHYMUX_TXV_MANUAL_V5_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TXV6 (0x82000000 + 0x3A5C)---

    CR_BAND1_PHYMUX_TXV_MANUAL_V6[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV6_CR_BAND1_PHYMUX_TXV_MANUAL_V6_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV6_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV6_CR_BAND1_PHYMUX_TXV_MANUAL_V6_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXV_MANUAL_V6[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TXV6_CR_BAND1_PHYMUX_TXV_MANUAL_V6_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TX_MODE_1 (0x82000000 + 0x3A60)---

    CR_BAND1_PHYMUX_TXD_MANUAL[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_1_CR_BAND1_PHYMUX_TXD_MANUAL_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_1_CR_BAND1_PHYMUX_TXD_MANUAL_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_TXD_MANUAL[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_1_CR_BAND1_PHYMUX_TXD_MANUAL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TX_MODE_2 (0x82000000 + 0x3A64)---

    CR_BAND1_PHYMUX_MANUAL_TXCNT[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_2_CR_BAND1_PHYMUX_MANUAL_TXCNT_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_2_CR_BAND1_PHYMUX_MANUAL_TXCNT_MASK 0x0000FFFF                // CR_BAND1_PHYMUX_MANUAL_TXCNT[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_2_CR_BAND1_PHYMUX_MANUAL_TXCNT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_TX_MODE_3 (0x82000000 + 0x3A68)---

    CR_BAND1_TEST_OUT[31..0]     - (RW) [DE] Test signal for forcing some phy2mac signal = 1
                                     [0]: force phy2mac_cca_prim = 1
                                     [1]: force phy2mac_cca_sec = 1
                                     [2]: force phy2mac_cca_sec40 = 1
                                     [3]: force phy2mac_txrdy = 1
                                     [4]: force phy2mac_txd_ack = 1
                                     [5]: force phy2mac_tx_err = 1
                                     [6]: force phy2mac_mdrdy = 1
                                     [7]: force phy2mac_rxd_vld = 1
                                     [8]: force phy2mac_rxair_end = 1
                                     [9]: force phy2mac_rx_err = 1
                                     [10]: force phy2mac_rxd_type = 1

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_3_CR_BAND1_TEST_OUT_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_3_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_3_CR_BAND1_TEST_OUT_MASK 0xFFFFFFFF                // CR_BAND1_TEST_OUT[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_TX_MODE_3_CR_BAND1_TEST_OUT_SHFT 0

/* =====================================================================================

  ---CR_BAND1_TXV_ERR_MASK (0x82000000 + 0x3A6C)---

    CR_BAND1_TXV_ERR_MASK[15..0] - (RO) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_TXV_ERR_MASK_CR_BAND1_TXV_ERR_MASK_ADDR WF_PHYRX_CTRL_CR_BAND1_TXV_ERR_MASK_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_TXV_ERR_MASK_CR_BAND1_TXV_ERR_MASK_MASK 0x0000FFFF                // CR_BAND1_TXV_ERR_MASK[15..0]
#define WF_PHYRX_CTRL_CR_BAND1_TXV_ERR_MASK_CR_BAND1_TXV_ERR_MASK_SHFT 0

/* =====================================================================================

  ---RO_BAND1_TXV_PKT_CNT (0x82000000 + 0x3A70)---

    RESERVED0[15..0]             - (RO) Reserved bits
    RO_BAND1_PHYMUX_TXV_PKT_CNT[31..16] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_PKT_CNT_RO_BAND1_PHYMUX_TXV_PKT_CNT_ADDR WF_PHYRX_CTRL_RO_BAND1_TXV_PKT_CNT_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_PKT_CNT_RO_BAND1_PHYMUX_TXV_PKT_CNT_MASK 0xFFFF0000                // RO_BAND1_PHYMUX_TXV_PKT_CNT[31..16]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_PKT_CNT_RO_BAND1_PHYMUX_TXV_PKT_CNT_SHFT 16

/* =====================================================================================

  ---RO_BAND1_TXV_1 (0x82000000 + 0x3A74)---

    RO_BAND1_TXV1[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_1_RO_BAND1_TXV1_ADDR        WF_PHYRX_CTRL_RO_BAND1_TXV_1_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_1_RO_BAND1_TXV1_MASK        0xFFFFFFFF                // RO_BAND1_TXV1[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_1_RO_BAND1_TXV1_SHFT        0

/* =====================================================================================

  ---RO_BAND1_TXV_2 (0x82000000 + 0x3A78)---

    RO_BAND1_TXV2[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_2_RO_BAND1_TXV2_ADDR        WF_PHYRX_CTRL_RO_BAND1_TXV_2_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_2_RO_BAND1_TXV2_MASK        0xFFFFFFFF                // RO_BAND1_TXV2[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_2_RO_BAND1_TXV2_SHFT        0

/* =====================================================================================

  ---RO_BAND1_TXV_3 (0x82000000 + 0x3A7C)---

    RO_BAND1_TXV3[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_3_RO_BAND1_TXV3_ADDR        WF_PHYRX_CTRL_RO_BAND1_TXV_3_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_3_RO_BAND1_TXV3_MASK        0xFFFFFFFF                // RO_BAND1_TXV3[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_3_RO_BAND1_TXV3_SHFT        0

/* =====================================================================================

  ---RO_BAND1_TXV_4 (0x82000000 + 0x3A80)---

    RO_BAND1_TXV4[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_4_RO_BAND1_TXV4_ADDR        WF_PHYRX_CTRL_RO_BAND1_TXV_4_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_4_RO_BAND1_TXV4_MASK        0xFFFFFFFF                // RO_BAND1_TXV4[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_4_RO_BAND1_TXV4_SHFT        0

/* =====================================================================================

  ---RO_BAND1_TXV_5 (0x82000000 + 0x3A84)---

    RO_BAND1_TXV5[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_5_RO_BAND1_TXV5_ADDR        WF_PHYRX_CTRL_RO_BAND1_TXV_5_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_5_RO_BAND1_TXV5_MASK        0xFFFFFFFF                // RO_BAND1_TXV5[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_5_RO_BAND1_TXV5_SHFT        0

/* =====================================================================================

  ---RO_BAND1_TXV_6 (0x82000000 + 0x3A88)---

    RO_BAND1_TXV6[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_6_RO_BAND1_TXV6_ADDR        WF_PHYRX_CTRL_RO_BAND1_TXV_6_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_6_RO_BAND1_TXV6_MASK        0xFFFFFFFF                // RO_BAND1_TXV6[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_6_RO_BAND1_TXV6_SHFT        0

/* =====================================================================================

  ---RO_BAND1_MANUAL_PHYMUX_TXD (0x82000000 + 0x3A8C)---

    RO_BAND1_TEST_TXD[31..0]     - (RO) [DE] observe mac2phy_txd

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_TXD_RO_BAND1_TEST_TXD_ADDR WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_TXD_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_TXD_RO_BAND1_TEST_TXD_MASK 0xFFFFFFFF                // RO_BAND1_TEST_TXD[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_TXD_RO_BAND1_TEST_TXD_SHFT 0

/* =====================================================================================

  ---RO_BAND1_MANUAL_PHYMUX_IN_0 (0x82000000 + 0x3A90)---

    RO_BAND1_TEST_IN[31..0]      - (RO) [DE] observe debug:
                                     [31:28]: {1'b0, mac2phy_disable_phy, mac2phy_tx, mac2phy_tx_rifs}
                                     [27:24]: {mac2phy_lpbcn, mac2phy_nav_ind, mac2phy_rx, mac2phy_rx_hold}
                                     [23:20]: mac2phy_measure_en[3:0]

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_0_RO_BAND1_TEST_IN_ADDR WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_0_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_0_RO_BAND1_TEST_IN_MASK 0xFFFFFFFF                // RO_BAND1_TEST_IN[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_0_RO_BAND1_TEST_IN_SHFT 0

/* =====================================================================================

  ---RO_BAND1_MANUAL_PHYMUX_IN_1 (0x82000000 + 0x3A94)---

    RO_BAND1_STS_IN[31..0]       - (RO) [DE] For debug: phy internal status

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_1_RO_BAND1_STS_IN_ADDR WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_1_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_1_RO_BAND1_STS_IN_MASK 0xFFFFFFFF                // RO_BAND1_STS_IN[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_MANUAL_PHYMUX_IN_1_RO_BAND1_STS_IN_SHFT 0

/* =====================================================================================

  ---RO_BAND1_TXV_ERR_MASK (0x82000000 + 0x3A98)---

    RESERVED0[15..0]             - (RO) Reserved bits
    RO_BAND1_TXV_ERR_FLAG[31..16] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_TXV_ERR_MASK_RO_BAND1_TXV_ERR_FLAG_ADDR WF_PHYRX_CTRL_RO_BAND1_TXV_ERR_MASK_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_TXV_ERR_MASK_RO_BAND1_TXV_ERR_FLAG_MASK 0xFFFF0000                // RO_BAND1_TXV_ERR_FLAG[31..16]
#define WF_PHYRX_CTRL_RO_BAND1_TXV_ERR_MASK_RO_BAND1_TXV_ERR_FLAG_SHFT 16

/* =====================================================================================

  ---CR_BAND1_RXV_SEL_0 (0x82000000 + 0x3AB0)---

    CR_BAND1_RXV_RXTD_SEL[1..0]  - (RW) [DE] BBP control CR
    CR_BAND1_RXV_WBRSSI_SEL[3..2] - (RW) [DE] BBP control CR
    CR_BAND1_RXV_IBRSSI_SEL[5..4] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RXV_RCPI_MODE[7..6] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RXV_LTF_SNR_EN[8] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RXV_SEL_G0[10..9] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RXV_SEL_G1[15..11] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RXV_SEL_G2[20..16] - (RW) [DE] BBP control CR
    CR_BAND1_RXV_DBG_SEL[24..21] - (RW) [DE] BBP control CR
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_DBG_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_DBG_SEL_MASK 0x01E00000                // CR_BAND1_RXV_DBG_SEL[24..21]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_DBG_SEL_SHFT 21
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G2_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G2_MASK 0x001F0000                // CR_BAND1_PHYMUX_RXV_SEL_G2[20..16]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G2_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G1_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G1_MASK 0x0000F800                // CR_BAND1_PHYMUX_RXV_SEL_G1[15..11]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G1_SHFT 11
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G0_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G0_MASK 0x00000600                // CR_BAND1_PHYMUX_RXV_SEL_G0[10..9]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_SEL_G0_SHFT 9
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_LTF_SNR_EN_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_LTF_SNR_EN_MASK 0x00000100                // CR_BAND1_PHYMUX_RXV_LTF_SNR_EN[8]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_LTF_SNR_EN_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_RCPI_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_RCPI_MODE_MASK 0x000000C0                // CR_BAND1_PHYMUX_RXV_RCPI_MODE[7..6]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_PHYMUX_RXV_RCPI_MODE_SHFT 6
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_IBRSSI_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_IBRSSI_SEL_MASK 0x00000030                // CR_BAND1_RXV_IBRSSI_SEL[5..4]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_IBRSSI_SEL_SHFT 4
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_WBRSSI_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_WBRSSI_SEL_MASK 0x0000000C                // CR_BAND1_RXV_WBRSSI_SEL[3..2]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_WBRSSI_SEL_SHFT 2
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_RXTD_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_RXTD_SEL_MASK 0x00000003                // CR_BAND1_RXV_RXTD_SEL[1..0]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_0_CR_BAND1_RXV_RXTD_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_RXV_SEL_1 (0x82000000 + 0x3AB4)---

    CR_BAND1_RXV_VEC3_SEL[7..0]  - (RW) [DE] BBP control CR
    CR_BAND1_RXV_VEC2_SEL[15..8] - (RW) [DE] BBP control CR
    CR_BAND1_RXV_VEC1_SEL[23..16] - (RW) [DE] BBP control CR
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC1_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC1_SEL_MASK 0x00FF0000                // CR_BAND1_RXV_VEC1_SEL[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC1_SEL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC2_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC2_SEL_MASK 0x0000FF00                // CR_BAND1_RXV_VEC2_SEL[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC2_SEL_SHFT 8
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC3_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC3_SEL_MASK 0x000000FF                // CR_BAND1_RXV_VEC3_SEL[7..0]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_1_CR_BAND1_RXV_VEC3_SEL_SHFT 0

/* =====================================================================================

  ---CR_BAND1_RXV_SEL_2 (0x82000000 + 0x3AB8)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_BAND1_RXV_VEC6_SEL[15..8] - (RW) [DE] BBP control CR
    CR_BAND1_RXV_VEC5_SEL[23..16] - (RW) [DE] BBP control CR
    CR_BAND1_RXV_VEC4_SEL[31..24] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC4_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC4_SEL_MASK 0xFF000000                // CR_BAND1_RXV_VEC4_SEL[31..24]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC4_SEL_SHFT 24
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC5_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC5_SEL_MASK 0x00FF0000                // CR_BAND1_RXV_VEC5_SEL[23..16]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC5_SEL_SHFT 16
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC6_SEL_ADDR WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC6_SEL_MASK 0x0000FF00                // CR_BAND1_RXV_VEC6_SEL[15..8]
#define WF_PHYRX_CTRL_CR_BAND1_RXV_SEL_2_CR_BAND1_RXV_VEC6_SEL_SHFT 8

/* =====================================================================================

  ---CR_BAND1_RXD_CTRL (0x82000000 + 0x3ABC)---

    CR_BAND1_PHYMUX_RXD_DLY[4..0] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RXD2RXV_DLY[9..5] - (RW) [DE] BBP control CR
    RESERVED10[31..10]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_CR_BAND1_PHYMUX_RXD2RXV_DLY_ADDR WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_CR_BAND1_PHYMUX_RXD2RXV_DLY_MASK 0x000003E0                // CR_BAND1_PHYMUX_RXD2RXV_DLY[9..5]
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_CR_BAND1_PHYMUX_RXD2RXV_DLY_SHFT 5
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_CR_BAND1_PHYMUX_RXD_DLY_ADDR WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_CR_BAND1_PHYMUX_RXD_DLY_MASK 0x0000001F                // CR_BAND1_PHYMUX_RXD_DLY[4..0]
#define WF_PHYRX_CTRL_CR_BAND1_RXD_CTRL_CR_BAND1_PHYMUX_RXD_DLY_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_RX_MODE_0 (0x82000000 + 0x3AC0)---

    CR_BAND1_PHYMUX_RX_MANUAL_ON[0] - (RW) [DE] BBP control CR
    CR_BAND1_PHYMUX_RX_MANUAL_MODE[1] - (RW) [DE] BBP control CR
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_CR_BAND1_PHYMUX_RX_MANUAL_MODE_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_CR_BAND1_PHYMUX_RX_MANUAL_MODE_MASK 0x00000002                // CR_BAND1_PHYMUX_RX_MANUAL_MODE[1]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_CR_BAND1_PHYMUX_RX_MANUAL_MODE_SHFT 1
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_CR_BAND1_PHYMUX_RX_MANUAL_ON_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_CR_BAND1_PHYMUX_RX_MANUAL_ON_MASK 0x00000001                // CR_BAND1_PHYMUX_RX_MANUAL_ON[0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_0_CR_BAND1_PHYMUX_RX_MANUAL_ON_SHFT 0

/* =====================================================================================

  ---CR_BAND1_MANUAL_PHYMUX_RX_MODE_1 (0x82000000 + 0x3AC4)---

    CR_BAND1_TEST_RXD[31..0]     - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_1_CR_BAND1_TEST_RXD_ADDR WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_1_CR_BAND1_TEST_RXD_MASK 0xFFFFFFFF                // CR_BAND1_TEST_RXD[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_MANUAL_PHYMUX_RX_MODE_1_CR_BAND1_TEST_RXD_SHFT 0

/* =====================================================================================

  ---RO_BAND1_RXV_0 (0x82000000 + 0x3AD0)---

    RO_BAND1_RXV_AFT1[31..0]     - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_0_RO_BAND1_RXV_AFT1_ADDR    WF_PHYRX_CTRL_RO_BAND1_RXV_0_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_0_RO_BAND1_RXV_AFT1_MASK    0xFFFFFFFF                // RO_BAND1_RXV_AFT1[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_0_RO_BAND1_RXV_AFT1_SHFT    0

/* =====================================================================================

  ---RO_BAND1_RXV_1 (0x82000000 + 0x3AD4)---

    RO_BAND1_RXV_AFT2[31..0]     - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_1_RO_BAND1_RXV_AFT2_ADDR    WF_PHYRX_CTRL_RO_BAND1_RXV_1_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_1_RO_BAND1_RXV_AFT2_MASK    0xFFFFFFFF                // RO_BAND1_RXV_AFT2[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_1_RO_BAND1_RXV_AFT2_SHFT    0

/* =====================================================================================

  ---RO_BAND1_RXV_2 (0x82000000 + 0x3AD8)---

    RO_BAND1_RXV_AFT3[31..0]     - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_2_RO_BAND1_RXV_AFT3_ADDR    WF_PHYRX_CTRL_RO_BAND1_RXV_2_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_2_RO_BAND1_RXV_AFT3_MASK    0xFFFFFFFF                // RO_BAND1_RXV_AFT3[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_2_RO_BAND1_RXV_AFT3_SHFT    0

/* =====================================================================================

  ---RO_BAND1_RXV_3 (0x82000000 + 0x3ADC)---

    RO_BAND1_RXV1[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_3_RO_BAND1_RXV1_ADDR        WF_PHYRX_CTRL_RO_BAND1_RXV_3_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_3_RO_BAND1_RXV1_MASK        0xFFFFFFFF                // RO_BAND1_RXV1[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_3_RO_BAND1_RXV1_SHFT        0

/* =====================================================================================

  ---RO_BAND1_RXV_4 (0x82000000 + 0x3AE0)---

    RO_BAND1_RXV2[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_4_RO_BAND1_RXV2_ADDR        WF_PHYRX_CTRL_RO_BAND1_RXV_4_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_4_RO_BAND1_RXV2_MASK        0xFFFFFFFF                // RO_BAND1_RXV2[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_4_RO_BAND1_RXV2_SHFT        0

/* =====================================================================================

  ---RO_BAND1_RXV_5 (0x82000000 + 0x3AE4)---

    RO_BAND1_RXV3[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_5_RO_BAND1_RXV3_ADDR        WF_PHYRX_CTRL_RO_BAND1_RXV_5_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_5_RO_BAND1_RXV3_MASK        0xFFFFFFFF                // RO_BAND1_RXV3[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_5_RO_BAND1_RXV3_SHFT        0

/* =====================================================================================

  ---RO_BAND1_RXV_6 (0x82000000 + 0x3AE8)---

    RO_BAND1_RXV4[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_6_RO_BAND1_RXV4_ADDR        WF_PHYRX_CTRL_RO_BAND1_RXV_6_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_6_RO_BAND1_RXV4_MASK        0xFFFFFFFF                // RO_BAND1_RXV4[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_6_RO_BAND1_RXV4_SHFT        0

/* =====================================================================================

  ---RO_BAND1_RXV_7 (0x82000000 + 0x3AEC)---

    RO_BAND1_RXV5[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_7_RO_BAND1_RXV5_ADDR        WF_PHYRX_CTRL_RO_BAND1_RXV_7_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_7_RO_BAND1_RXV5_MASK        0xFFFFFFFF                // RO_BAND1_RXV5[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_7_RO_BAND1_RXV5_SHFT        0

/* =====================================================================================

  ---RO_BAND1_RXV_8 (0x82000000 + 0x3AF0)---

    RO_BAND1_RXV6[31..0]         - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND1_RXV_8_RO_BAND1_RXV6_ADDR        WF_PHYRX_CTRL_RO_BAND1_RXV_8_ADDR
#define WF_PHYRX_CTRL_RO_BAND1_RXV_8_RO_BAND1_RXV6_MASK        0xFFFFFFFF                // RO_BAND1_RXV6[31..0]
#define WF_PHYRX_CTRL_RO_BAND1_RXV_8_RO_BAND1_RXV6_SHFT        0

/* =====================================================================================

  ---CR_BAND1_PHYMUX_RSVD0 (0x82000000 + 0x3B00)---

    CR_BAND1_PHYMUX_RSVD0[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD0_CR_BAND1_PHYMUX_RSVD0_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD0_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD0_CR_BAND1_PHYMUX_RSVD0_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_RSVD0[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD0_CR_BAND1_PHYMUX_RSVD0_SHFT 0

/* =====================================================================================

  ---CR_BAND1_PHYMUX_RSVD1 (0x82000000 + 0x3B04)---

    CR_BAND1_PHYMUX_RSVD1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD1_CR_BAND1_PHYMUX_RSVD1_ADDR WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD1_ADDR
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD1_CR_BAND1_PHYMUX_RSVD1_MASK 0xFFFFFFFF                // CR_BAND1_PHYMUX_RSVD1[31..0]
#define WF_PHYRX_CTRL_CR_BAND1_PHYMUX_RSVD1_CR_BAND1_PHYMUX_RSVD1_SHFT 0

/* =====================================================================================

  ---CR_MBIST_CTRL (0x82000000 + 0x4000)---

    CR_MBIST_SLEEP_TEST[0]       - (RW) [DE] BBP control CR
    CR_MBIST_SLEEP_R[1]          - (RW) [DE] BBP control CR
    CR_MBIST_SLEEP_W[2]          - (RW) [DE] BBP control CR
    CR_MBIST_SLEEP_INV[3]        - (RW) [DE] BBP control CR
    RESERVED4[28..4]             - (RO) Reserved bits
    CR_MBIST_DEBUG[29]           - (RW) [DE] BBP control CR
    CR_MBIST_HOLDB[30]           - (RW) [DE] BBP control CR
    CR_MBIST_RSTB[31]            - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_RSTB_ADDR         WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_RSTB_MASK         0x80000000                // CR_MBIST_RSTB[31]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_RSTB_SHFT         31
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_HOLDB_ADDR        WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_HOLDB_MASK        0x40000000                // CR_MBIST_HOLDB[30]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_HOLDB_SHFT        30
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_DEBUG_ADDR        WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_DEBUG_MASK        0x20000000                // CR_MBIST_DEBUG[29]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_DEBUG_SHFT        29
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_INV_ADDR    WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_INV_MASK    0x00000008                // CR_MBIST_SLEEP_INV[3]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_INV_SHFT    3
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_W_ADDR      WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_W_MASK      0x00000004                // CR_MBIST_SLEEP_W[2]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_W_SHFT      2
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_R_ADDR      WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_R_MASK      0x00000002                // CR_MBIST_SLEEP_R[1]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_R_SHFT      1
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_TEST_ADDR   WF_PHYRX_CTRL_CR_MBIST_CTRL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_TEST_MASK   0x00000001                // CR_MBIST_SLEEP_TEST[0]
#define WF_PHYRX_CTRL_CR_MBIST_CTRL_CR_MBIST_SLEEP_TEST_SHFT   0

/* =====================================================================================

  ---CR_MBIST_DIAG (0x82000000 + 0x4004)---

    CR_MBIST_DIAG_SCAN_OUT_SEL[15..0] - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_DIAG_CR_MBIST_DIAG_SCAN_OUT_SEL_ADDR WF_PHYRX_CTRL_CR_MBIST_DIAG_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_DIAG_CR_MBIST_DIAG_SCAN_OUT_SEL_MASK 0x0000FFFF                // CR_MBIST_DIAG_SCAN_OUT_SEL[15..0]
#define WF_PHYRX_CTRL_CR_MBIST_DIAG_CR_MBIST_DIAG_SCAN_OUT_SEL_SHFT 0

/* =====================================================================================

  ---CR_MBIST_BSEL (0x82000000 + 0x4008)---

    CR_MBIST_BSEL[31..0]         - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_BSEL_CR_MBIST_BSEL_ADDR         WF_PHYRX_CTRL_CR_MBIST_BSEL_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_BSEL_CR_MBIST_BSEL_MASK         0xFFFFFFFF                // CR_MBIST_BSEL[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_BSEL_CR_MBIST_BSEL_SHFT         0

/* =====================================================================================

  ---CR_MBIST_BACKGROUND (0x82000000 + 0x400C)---

    CR_MBIST_BACKGROUND[15..0]   - (RW) [DE] BBP control CR
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_BACKGROUND_CR_MBIST_BACKGROUND_ADDR WF_PHYRX_CTRL_CR_MBIST_BACKGROUND_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_BACKGROUND_CR_MBIST_BACKGROUND_MASK 0x0000FFFF                // CR_MBIST_BACKGROUND[15..0]
#define WF_PHYRX_CTRL_CR_MBIST_BACKGROUND_CR_MBIST_BACKGROUND_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MODE_0 (0x82000000 + 0x4020)---

    CR_MBIST_MODE_0[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MODE_0_CR_MBIST_MODE_0_ADDR     WF_PHYRX_CTRL_CR_MBIST_MODE_0_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MODE_0_CR_MBIST_MODE_0_MASK     0xFFFFFFFF                // CR_MBIST_MODE_0[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MODE_0_CR_MBIST_MODE_0_SHFT     0

/* =====================================================================================

  ---CR_MBIST_MODE_1 (0x82000000 + 0x4024)---

    CR_MBIST_MODE_1[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MODE_1_CR_MBIST_MODE_1_ADDR     WF_PHYRX_CTRL_CR_MBIST_MODE_1_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MODE_1_CR_MBIST_MODE_1_MASK     0xFFFFFFFF                // CR_MBIST_MODE_1[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MODE_1_CR_MBIST_MODE_1_SHFT     0

/* =====================================================================================

  ---CR_MBIST_MODE_2 (0x82000000 + 0x4028)---

    CR_MBIST_MODE_2[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MODE_2_CR_MBIST_MODE_2_ADDR     WF_PHYRX_CTRL_CR_MBIST_MODE_2_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MODE_2_CR_MBIST_MODE_2_MASK     0xFFFFFFFF                // CR_MBIST_MODE_2[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MODE_2_CR_MBIST_MODE_2_SHFT     0

/* =====================================================================================

  ---CR_MBIST_MODE_3 (0x82000000 + 0x402C)---

    CR_MBIST_MODE_3[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MODE_3_CR_MBIST_MODE_3_ADDR     WF_PHYRX_CTRL_CR_MBIST_MODE_3_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MODE_3_CR_MBIST_MODE_3_MASK     0xFFFFFFFF                // CR_MBIST_MODE_3[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MODE_3_CR_MBIST_MODE_3_SHFT     0

/* =====================================================================================

  ---CR_MBIST_MODE_4 (0x82000000 + 0x4030)---

    CR_MBIST_MODE_4[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MODE_4_CR_MBIST_MODE_4_ADDR     WF_PHYRX_CTRL_CR_MBIST_MODE_4_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MODE_4_CR_MBIST_MODE_4_MASK     0xFFFFFFFF                // CR_MBIST_MODE_4[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MODE_4_CR_MBIST_MODE_4_SHFT     0

/* =====================================================================================

  ---CR_MBIST_MODE_5 (0x82000000 + 0x4034)---

    CR_MBIST_MODE_5[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MODE_5_CR_MBIST_MODE_5_ADDR     WF_PHYRX_CTRL_CR_MBIST_MODE_5_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MODE_5_CR_MBIST_MODE_5_MASK     0xFFFFFFFF                // CR_MBIST_MODE_5[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MODE_5_CR_MBIST_MODE_5_SHFT     0

/* =====================================================================================

  ---RO_MBIST_DONE_0 (0x82000000 + 0x4040)---

    RO_MBIST_DONE_STATUS_0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_DONE_0_RO_MBIST_DONE_STATUS_0_ADDR WF_PHYRX_CTRL_RO_MBIST_DONE_0_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_DONE_0_RO_MBIST_DONE_STATUS_0_MASK 0xFFFFFFFF                // RO_MBIST_DONE_STATUS_0[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_DONE_0_RO_MBIST_DONE_STATUS_0_SHFT 0

/* =====================================================================================

  ---RO_MBIST_DONE_1 (0x82000000 + 0x4044)---

    RO_MBIST_DONE_STATUS_1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_DONE_1_RO_MBIST_DONE_STATUS_1_ADDR WF_PHYRX_CTRL_RO_MBIST_DONE_1_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_DONE_1_RO_MBIST_DONE_STATUS_1_MASK 0xFFFFFFFF                // RO_MBIST_DONE_STATUS_1[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_DONE_1_RO_MBIST_DONE_STATUS_1_SHFT 0

/* =====================================================================================

  ---RO_MBIST_DONE_2 (0x82000000 + 0x4048)---

    RO_MBIST_DONE_STATUS_2[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_DONE_2_RO_MBIST_DONE_STATUS_2_ADDR WF_PHYRX_CTRL_RO_MBIST_DONE_2_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_DONE_2_RO_MBIST_DONE_STATUS_2_MASK 0xFFFFFFFF                // RO_MBIST_DONE_STATUS_2[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_DONE_2_RO_MBIST_DONE_STATUS_2_SHFT 0

/* =====================================================================================

  ---RO_MBIST_DONE_3 (0x82000000 + 0x404C)---

    RO_MBIST_DONE_STATUS_3[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_DONE_3_RO_MBIST_DONE_STATUS_3_ADDR WF_PHYRX_CTRL_RO_MBIST_DONE_3_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_DONE_3_RO_MBIST_DONE_STATUS_3_MASK 0xFFFFFFFF                // RO_MBIST_DONE_STATUS_3[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_DONE_3_RO_MBIST_DONE_STATUS_3_SHFT 0

/* =====================================================================================

  ---RO_MBIST_DONE_4 (0x82000000 + 0x4050)---

    RO_MBIST_DONE_STATUS_4[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_DONE_4_RO_MBIST_DONE_STATUS_4_ADDR WF_PHYRX_CTRL_RO_MBIST_DONE_4_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_DONE_4_RO_MBIST_DONE_STATUS_4_MASK 0xFFFFFFFF                // RO_MBIST_DONE_STATUS_4[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_DONE_4_RO_MBIST_DONE_STATUS_4_SHFT 0

/* =====================================================================================

  ---RO_MBIST_DONE_5 (0x82000000 + 0x4054)---

    RO_MBIST_DONE_STATUS_5[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_DONE_5_RO_MBIST_DONE_STATUS_5_ADDR WF_PHYRX_CTRL_RO_MBIST_DONE_5_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_DONE_5_RO_MBIST_DONE_STATUS_5_MASK 0xFFFFFFFF                // RO_MBIST_DONE_STATUS_5[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_DONE_5_RO_MBIST_DONE_STATUS_5_SHFT 0

/* =====================================================================================

  ---RO_MBIST_FAIL_0 (0x82000000 + 0x4060)---

    RO_MBIST_FAIL_STATUS_0[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_0_RO_MBIST_FAIL_STATUS_0_ADDR WF_PHYRX_CTRL_RO_MBIST_FAIL_0_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_0_RO_MBIST_FAIL_STATUS_0_MASK 0xFFFFFFFF                // RO_MBIST_FAIL_STATUS_0[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_0_RO_MBIST_FAIL_STATUS_0_SHFT 0

/* =====================================================================================

  ---RO_MBIST_FAIL_1 (0x82000000 + 0x4064)---

    RO_MBIST_FAIL_STATUS_1[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_1_RO_MBIST_FAIL_STATUS_1_ADDR WF_PHYRX_CTRL_RO_MBIST_FAIL_1_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_1_RO_MBIST_FAIL_STATUS_1_MASK 0xFFFFFFFF                // RO_MBIST_FAIL_STATUS_1[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_1_RO_MBIST_FAIL_STATUS_1_SHFT 0

/* =====================================================================================

  ---RO_MBIST_FAIL_2 (0x82000000 + 0x4068)---

    RO_MBIST_FAIL_STATUS_2[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_2_RO_MBIST_FAIL_STATUS_2_ADDR WF_PHYRX_CTRL_RO_MBIST_FAIL_2_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_2_RO_MBIST_FAIL_STATUS_2_MASK 0xFFFFFFFF                // RO_MBIST_FAIL_STATUS_2[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_2_RO_MBIST_FAIL_STATUS_2_SHFT 0

/* =====================================================================================

  ---RO_MBIST_FAIL_3 (0x82000000 + 0x406C)---

    RO_MBIST_FAIL_STATUS_3[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_3_RO_MBIST_FAIL_STATUS_3_ADDR WF_PHYRX_CTRL_RO_MBIST_FAIL_3_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_3_RO_MBIST_FAIL_STATUS_3_MASK 0xFFFFFFFF                // RO_MBIST_FAIL_STATUS_3[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_3_RO_MBIST_FAIL_STATUS_3_SHFT 0

/* =====================================================================================

  ---RO_MBIST_FAIL_4 (0x82000000 + 0x4070)---

    RO_MBIST_FAIL_STATUS_4[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_4_RO_MBIST_FAIL_STATUS_4_ADDR WF_PHYRX_CTRL_RO_MBIST_FAIL_4_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_4_RO_MBIST_FAIL_STATUS_4_MASK 0xFFFFFFFF                // RO_MBIST_FAIL_STATUS_4[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_4_RO_MBIST_FAIL_STATUS_4_SHFT 0

/* =====================================================================================

  ---RO_MBIST_FAIL_5 (0x82000000 + 0x4074)---

    RO_MBIST_FAIL_STATUS_5[31..0] - (RO) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_5_RO_MBIST_FAIL_STATUS_5_ADDR WF_PHYRX_CTRL_RO_MBIST_FAIL_5_ADDR
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_5_RO_MBIST_FAIL_STATUS_5_MASK 0xFFFFFFFF                // RO_MBIST_FAIL_STATUS_5[31..0]
#define WF_PHYRX_CTRL_RO_MBIST_FAIL_5_RO_MBIST_FAIL_STATUS_5_SHFT 0

/* =====================================================================================

  ---CR_USE_DEFAULT_DELSEL_0 (0x82000000 + 0x4080)---

    CR_USE_DEFAULT_DELSEL_0[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_0_CR_USE_DEFAULT_DELSEL_0_ADDR WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_0_ADDR
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_0_CR_USE_DEFAULT_DELSEL_0_MASK 0xFFFFFFFF                // CR_USE_DEFAULT_DELSEL_0[31..0]
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_0_CR_USE_DEFAULT_DELSEL_0_SHFT 0

/* =====================================================================================

  ---CR_USE_DEFAULT_DELSEL_1 (0x82000000 + 0x4084)---

    CR_USE_DEFAULT_DELSEL_1[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_1_CR_USE_DEFAULT_DELSEL_1_ADDR WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_1_ADDR
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_1_CR_USE_DEFAULT_DELSEL_1_MASK 0xFFFFFFFF                // CR_USE_DEFAULT_DELSEL_1[31..0]
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_1_CR_USE_DEFAULT_DELSEL_1_SHFT 0

/* =====================================================================================

  ---CR_USE_DEFAULT_DELSEL_2 (0x82000000 + 0x4088)---

    CR_USE_DEFAULT_DELSEL_2[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_2_CR_USE_DEFAULT_DELSEL_2_ADDR WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_2_ADDR
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_2_CR_USE_DEFAULT_DELSEL_2_MASK 0xFFFFFFFF                // CR_USE_DEFAULT_DELSEL_2[31..0]
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_2_CR_USE_DEFAULT_DELSEL_2_SHFT 0

/* =====================================================================================

  ---CR_USE_DEFAULT_DELSEL_3 (0x82000000 + 0x408C)---

    CR_USE_DEFAULT_DELSEL_3[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_3_CR_USE_DEFAULT_DELSEL_3_ADDR WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_3_ADDR
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_3_CR_USE_DEFAULT_DELSEL_3_MASK 0xFFFFFFFF                // CR_USE_DEFAULT_DELSEL_3[31..0]
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_3_CR_USE_DEFAULT_DELSEL_3_SHFT 0

/* =====================================================================================

  ---CR_USE_DEFAULT_DELSEL_4 (0x82000000 + 0x4090)---

    CR_USE_DEFAULT_DELSEL_4[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_4_CR_USE_DEFAULT_DELSEL_4_ADDR WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_4_ADDR
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_4_CR_USE_DEFAULT_DELSEL_4_MASK 0xFFFFFFFF                // CR_USE_DEFAULT_DELSEL_4[31..0]
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_4_CR_USE_DEFAULT_DELSEL_4_SHFT 0

/* =====================================================================================

  ---CR_USE_DEFAULT_DELSEL_5 (0x82000000 + 0x4094)---

    CR_USE_DEFAULT_DELSEL_5[31..0] - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_5_CR_USE_DEFAULT_DELSEL_5_ADDR WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_5_ADDR
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_5_CR_USE_DEFAULT_DELSEL_5_MASK 0xFFFFFFFF                // CR_USE_DEFAULT_DELSEL_5[31..0]
#define WF_PHYRX_CTRL_CR_USE_DEFAULT_DELSEL_5_CR_USE_DEFAULT_DELSEL_5_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_0 (0x82000000 + 0x4200)---

    CR_MEM_DELSEL_0[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_0_CR_MEM_DELSEL_0_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_0_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_0_CR_MEM_DELSEL_0_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_0[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_0_CR_MEM_DELSEL_0_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_1 (0x82000000 + 0x4204)---

    CR_MEM_DELSEL_1[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_1_CR_MEM_DELSEL_1_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_1_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_1_CR_MEM_DELSEL_1_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_1[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_1_CR_MEM_DELSEL_1_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_2 (0x82000000 + 0x4208)---

    CR_MEM_DELSEL_2[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_2_CR_MEM_DELSEL_2_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_2_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_2_CR_MEM_DELSEL_2_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_2[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_2_CR_MEM_DELSEL_2_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_3 (0x82000000 + 0x420C)---

    CR_MEM_DELSEL_3[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_3_CR_MEM_DELSEL_3_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_3_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_3_CR_MEM_DELSEL_3_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_3[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_3_CR_MEM_DELSEL_3_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_4 (0x82000000 + 0x4210)---

    CR_MEM_DELSEL_4[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_4_CR_MEM_DELSEL_4_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_4_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_4_CR_MEM_DELSEL_4_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_4[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_4_CR_MEM_DELSEL_4_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_5 (0x82000000 + 0x4214)---

    CR_MEM_DELSEL_5[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_5_CR_MEM_DELSEL_5_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_5_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_5_CR_MEM_DELSEL_5_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_5[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_5_CR_MEM_DELSEL_5_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_6 (0x82000000 + 0x4218)---

    CR_MEM_DELSEL_6[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_6_CR_MEM_DELSEL_6_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_6_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_6_CR_MEM_DELSEL_6_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_6[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_6_CR_MEM_DELSEL_6_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_7 (0x82000000 + 0x421C)---

    CR_MEM_DELSEL_7[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_7_CR_MEM_DELSEL_7_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_7_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_7_CR_MEM_DELSEL_7_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_7[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_7_CR_MEM_DELSEL_7_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_8 (0x82000000 + 0x4220)---

    CR_MEM_DELSEL_8[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_8_CR_MEM_DELSEL_8_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_8_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_8_CR_MEM_DELSEL_8_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_8[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_8_CR_MEM_DELSEL_8_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_9 (0x82000000 + 0x4224)---

    CR_MEM_DELSEL_9[31..0]       - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_9_CR_MEM_DELSEL_9_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_9_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_9_CR_MEM_DELSEL_9_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_9[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_9_CR_MEM_DELSEL_9_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_10 (0x82000000 + 0x4228)---

    CR_MEM_DELSEL_10[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_10_CR_MEM_DELSEL_10_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_10_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_10_CR_MEM_DELSEL_10_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_10[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_10_CR_MEM_DELSEL_10_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_11 (0x82000000 + 0x422C)---

    CR_MEM_DELSEL_11[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_11_CR_MEM_DELSEL_11_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_11_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_11_CR_MEM_DELSEL_11_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_11[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_11_CR_MEM_DELSEL_11_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_12 (0x82000000 + 0x4230)---

    CR_MEM_DELSEL_12[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_12_CR_MEM_DELSEL_12_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_12_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_12_CR_MEM_DELSEL_12_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_12[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_12_CR_MEM_DELSEL_12_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_13 (0x82000000 + 0x4234)---

    CR_MEM_DELSEL_13[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_13_CR_MEM_DELSEL_13_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_13_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_13_CR_MEM_DELSEL_13_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_13[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_13_CR_MEM_DELSEL_13_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_14 (0x82000000 + 0x4238)---

    CR_MEM_DELSEL_14[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_14_CR_MEM_DELSEL_14_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_14_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_14_CR_MEM_DELSEL_14_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_14[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_14_CR_MEM_DELSEL_14_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_15 (0x82000000 + 0x423C)---

    CR_MEM_DELSEL_15[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_15_CR_MEM_DELSEL_15_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_15_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_15_CR_MEM_DELSEL_15_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_15[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_15_CR_MEM_DELSEL_15_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_16 (0x82000000 + 0x4240)---

    CR_MEM_DELSEL_16[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_16_CR_MEM_DELSEL_16_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_16_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_16_CR_MEM_DELSEL_16_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_16[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_16_CR_MEM_DELSEL_16_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_17 (0x82000000 + 0x4244)---

    CR_MEM_DELSEL_17[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_17_CR_MEM_DELSEL_17_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_17_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_17_CR_MEM_DELSEL_17_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_17[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_17_CR_MEM_DELSEL_17_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_18 (0x82000000 + 0x4248)---

    CR_MEM_DELSEL_18[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_18_CR_MEM_DELSEL_18_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_18_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_18_CR_MEM_DELSEL_18_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_18[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_18_CR_MEM_DELSEL_18_SHFT 0

/* =====================================================================================

  ---CR_MBIST_MEM_DELSEL_19 (0x82000000 + 0x424C)---

    CR_MEM_DELSEL_19[31..0]      - (RW) [DE] BBP control CR

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_19_CR_MEM_DELSEL_19_ADDR WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_19_ADDR
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_19_CR_MEM_DELSEL_19_MASK 0xFFFFFFFF                // CR_MEM_DELSEL_19[31..0]
#define WF_PHYRX_CTRL_CR_MBIST_MEM_DELSEL_19_CR_MEM_DELSEL_19_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2M_PHY_INTF (0x82000000 + 0x4700)---

    cr_band0_m2mpif_tx_manual_mode[31..0] - (RW) [31] 0: HW Mode, 1: Manual Mode
                                     [30:0] Manaul mode value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2M_PHY_INTF_cr_band0_m2mpif_tx_manual_mode_ADDR WF_PHYRX_CTRL_CR_BAND0_M2M_PHY_INTF_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2M_PHY_INTF_cr_band0_m2mpif_tx_manual_mode_MASK 0xFFFFFFFF                // cr_band0_m2mpif_tx_manual_mode[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2M_PHY_INTF_cr_band0_m2mpif_tx_manual_mode_SHFT 0

/* =====================================================================================

  ---RO_BAND0_M2M_PHY_INTF (0x82000000 + 0x4704)---

    ro_band0_m2mpif_rx_in_bus[31..0] - (RO) ro_band0_m2mpif_rx_in_bus

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_M2M_PHY_INTF_ro_band0_m2mpif_rx_in_bus_ADDR WF_PHYRX_CTRL_RO_BAND0_M2M_PHY_INTF_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_M2M_PHY_INTF_ro_band0_m2mpif_rx_in_bus_MASK 0xFFFFFFFF                // ro_band0_m2mpif_rx_in_bus[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_M2M_PHY_INTF_ro_band0_m2mpif_rx_in_bus_SHFT 0

/* =====================================================================================

  ---RO_BAND0_M2M_RX_DBG_STATUS (0x82000000 + 0x4708)---

    ro_band0_m2m_rx_dbg_status[31..0] - (RO) ro_band0_m2m_rx_dbg_status

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_M2M_RX_DBG_STATUS_ro_band0_m2m_rx_dbg_status_ADDR WF_PHYRX_CTRL_RO_BAND0_M2M_RX_DBG_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_M2M_RX_DBG_STATUS_ro_band0_m2m_rx_dbg_status_MASK 0xFFFFFFFF                // ro_band0_m2m_rx_dbg_status[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_M2M_RX_DBG_STATUS_ro_band0_m2m_rx_dbg_status_SHFT 0

/* =====================================================================================

  ---RO_BAND0_M2M_TX_DBG_STATUS (0x82000000 + 0x470C)---

    ro_band0_m2m_tx_dbg_status[31..0] - (RO) ro_band0_m2m_tx_dbg_status

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BAND0_M2M_TX_DBG_STATUS_ro_band0_m2m_tx_dbg_status_ADDR WF_PHYRX_CTRL_RO_BAND0_M2M_TX_DBG_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_BAND0_M2M_TX_DBG_STATUS_ro_band0_m2m_tx_dbg_status_MASK 0xFFFFFFFF                // ro_band0_m2m_tx_dbg_status[31..0]
#define WF_PHYRX_CTRL_RO_BAND0_M2M_TX_DBG_STATUS_ro_band0_m2m_tx_dbg_status_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_RXV3 (0x82000000 + 0x4720)---

    cr_band0_m2mp_rxv3[31..0]    - (RW) [31:0] M2M_PHY RXV Value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV3_cr_band0_m2mp_rxv3_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV3_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV3_cr_band0_m2mp_rxv3_MASK 0xFFFFFFFF                // cr_band0_m2mp_rxv3[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV3_cr_band0_m2mp_rxv3_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_RXV4 (0x82000000 + 0x4724)---

    cr_band0_m2mp_rxv4[31..0]    - (RW) [31:0] M2M_PHY RXV Value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV4_cr_band0_m2mp_rxv4_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV4_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV4_cr_band0_m2mp_rxv4_MASK 0xFFFFFFFF                // cr_band0_m2mp_rxv4[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV4_cr_band0_m2mp_rxv4_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_RXV5 (0x82000000 + 0x4728)---

    cr_band0_m2mp_rxv5[31..0]    - (RW) [31:0] M2M_PHY RXV Value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV5_cr_band0_m2mp_rxv5_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV5_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV5_cr_band0_m2mp_rxv5_MASK 0xFFFFFFFF                // cr_band0_m2mp_rxv5[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV5_cr_band0_m2mp_rxv5_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_RXV6 (0x82000000 + 0x472C)---

    cr_band0_m2mp_rxv6[31..0]    - (RW) [31:0] M2M_PHY RXV Value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV6_cr_band0_m2mp_rxv6_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV6_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV6_cr_band0_m2mp_rxv6_MASK 0xFFFFFFFF                // cr_band0_m2mp_rxv6[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_RXV6_cr_band0_m2mp_rxv6_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_AFT_RXV1 (0x82000000 + 0x4730)---

    cr_band0_m2mp_aft_rxv1[31..0] - (RW) [31:0] M2M_PHY RXV Value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV1_cr_band0_m2mp_aft_rxv1_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV1_cr_band0_m2mp_aft_rxv1_MASK 0xFFFFFFFF                // cr_band0_m2mp_aft_rxv1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV1_cr_band0_m2mp_aft_rxv1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_AFT_RXV2 (0x82000000 + 0x4734)---

    cr_band0_m2mp_aft_rxv2[31..0] - (RW) [31:0] M2M_PHY RXV Value

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV2_cr_band0_m2mp_aft_rxv2_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV2_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV2_cr_band0_m2mp_aft_rxv2_MASK 0xFFFFFFFF                // cr_band0_m2mp_aft_rxv2[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_AFT_RXV2_cr_band0_m2mp_aft_rxv2_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_CCK_PER (0x82000000 + 0x4738)---

    cr_band0_m2mp_cck_per[31..0] - (RW) [31:0] M2M_PHY RX CCK_PER

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_CCK_PER_cr_band0_m2mp_cck_per_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_CCK_PER_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_CCK_PER_cr_band0_m2mp_cck_per_MASK 0xFFFFFFFF                // cr_band0_m2mp_cck_per[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_CCK_PER_cr_band0_m2mp_cck_per_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_LG_PER (0x82000000 + 0x473C)---

    cr_band0_m2mp_lg_per[31..0]  - (RW) [31:0] M2M_PHY RX LG_PER

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_LG_PER_cr_band0_m2mp_lg_per_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_LG_PER_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_LG_PER_cr_band0_m2mp_lg_per_MASK 0xFFFFFFFF                // cr_band0_m2mp_lg_per[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_LG_PER_cr_band0_m2mp_lg_per_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_HT20_PER0 (0x82000000 + 0x4740)---

    cr_band0_m2mp_ht20_per0[31..0] - (RW) [31:0] M2M_PHY RX HT20_PER0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER0_cr_band0_m2mp_ht20_per0_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER0_cr_band0_m2mp_ht20_per0_MASK 0xFFFFFFFF                // cr_band0_m2mp_ht20_per0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER0_cr_band0_m2mp_ht20_per0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_HT20_PER1 (0x82000000 + 0x4744)---

    cr_band0_m2mp_ht20_per1[31..0] - (RW) [31:0] M2M_PHY RX HT20_PER1

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER1_cr_band0_m2mp_ht20_per1_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER1_cr_band0_m2mp_ht20_per1_MASK 0xFFFFFFFF                // cr_band0_m2mp_ht20_per1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT20_PER1_cr_band0_m2mp_ht20_per1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_HT40_PER0 (0x82000000 + 0x4748)---

    cr_band0_m2mp_ht40_per0[31..0] - (RW) [31:0] M2M_PHY RX HT40_PER0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER0_cr_band0_m2mp_ht40_per0_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER0_cr_band0_m2mp_ht40_per0_MASK 0xFFFFFFFF                // cr_band0_m2mp_ht40_per0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER0_cr_band0_m2mp_ht40_per0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_HT40_PER1 (0x82000000 + 0x474C)---

    cr_band0_m2mp_ht40_per1[31..0] - (RW) [31:0] M2M_PHY RX HT40_PER1

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER1_cr_band0_m2mp_ht40_per1_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER1_cr_band0_m2mp_ht40_per1_MASK 0xFFFFFFFF                // cr_band0_m2mp_ht40_per1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_HT40_PER1_cr_band0_m2mp_ht40_per1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_VHT80_PER0 (0x82000000 + 0x4750)---

    cr_band0_m2mp_vht80_per0[31..0] - (RW) [31:0] M2M_PHY RX VHT80_PER0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER0_cr_band0_m2mp_vht80_per0_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER0_cr_band0_m2mp_vht80_per0_MASK 0xFFFFFFFF                // cr_band0_m2mp_vht80_per0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER0_cr_band0_m2mp_vht80_per0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_VHT80_PER1 (0x82000000 + 0x4754)---

    cr_band0_m2mp_vht80_per1[31..0] - (RW) [31:0] M2M_PHY RX VHT80_PER1

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER1_cr_band0_m2mp_vht80_per1_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER1_cr_band0_m2mp_vht80_per1_MASK 0xFFFFFFFF                // cr_band0_m2mp_vht80_per1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT80_PER1_cr_band0_m2mp_vht80_per1_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_VHT160_PER0 (0x82000000 + 0x4758)---

    cr_band0_m2mp_vht160_per0[31..0] - (RW) [31:0] M2M_PHY RX VHT160_PER0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER0_cr_band0_m2mp_vht160_per0_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER0_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER0_cr_band0_m2mp_vht160_per0_MASK 0xFFFFFFFF                // cr_band0_m2mp_vht160_per0[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER0_cr_band0_m2mp_vht160_per0_SHFT 0

/* =====================================================================================

  ---CR_BAND0_M2MP_VHT160_PER1 (0x82000000 + 0x475C)---

    cr_band0_m2mp_vht160_per1[31..0] - (RW) [31:0] M2M_PHY RX VHT160_PER1

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER1_cr_band0_m2mp_vht160_per1_ADDR WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER1_ADDR
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER1_cr_band0_m2mp_vht160_per1_MASK 0xFFFFFFFF                // cr_band0_m2mp_vht160_per1[31..0]
#define WF_PHYRX_CTRL_CR_BAND0_M2MP_VHT160_PER1_cr_band0_m2mp_vht160_per1_SHFT 0

/* =====================================================================================

  ---CR_BF_CONTROL (0x82000000 + 0x4800)---

    CR_BAND0_RX_EBF_EN[0]        - (RW) [DE] Enable RX/SVD NDP calculation on Band0
    CR_BAND0_RX_IBF_EN[1]        - (RW) [DE] Enable RX/SVD iBF calculation on Band0
    CR_BAND1_RX_EBF_EN[2]        - (RW) [DE] Enable RX/SVD NDP calculation on Band1
    CR_BAND1_RX_IBF_EN[3]        - (RW) [DE] Enable RX/SVD iBF calculation on Band1
    CR_BF_DBDC_BAND_SEL[4]       - (RW) [DE] Beamform band selection on DBDC mode
                                     0: Support BF on Band0
                                     1: Support BF on Band1
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_PFMU_SWAP_SEG_EN[8]       - (RW) [CSD] Swap 160NC segment0/1 data on BFee_s side.
                                     If CBW=160C, this bit must be set to 0, otherwise it will also swap segments.
    RESERVED9[12..9]             - (RO) Reserved bits
    CR_BFOFF_ENB_3BF3SS[13]      - (RW) [CSD] turn off BF if Nr = Nsts = 3
    CR_BFOFF_ENB_2BF2SS[14]      - (RW) [CSD] turn off BF if Nr = Nsts = 2
    CR_BFTX_ROLLBACK_ENB[15]     - (RW) [CSD] rollback to disable processing 4x4 profile
    CR_BF_BFEE_FORCE_ANGLE_EN[16] - (RW) [CSD] Force angles on PFMU BFee side
    CR_BF_BFER_FORCE_ANGLE_EN[17] - (RW) [CSD] Force angles on PFMU BFer side
    CR_MAN_TXBF_STA[19..18]      - (RW) [DE] manual set txbf_sta to force apply eBF for continous TX
    CR_MAN_TXBF_STA_VLD[20]      - (RW) [DE] manual set txbf_sta_vld to force apply eBF for continous TX
    CR_MAN_TXFD_PF_LOOKUP[21]    - (RW) [DE] force to trigger PFMU/MUTX to calculate BF matrix for continous TX
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXFD_PF_LOOKUP_ADDR WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXFD_PF_LOOKUP_MASK 0x00200000                // CR_MAN_TXFD_PF_LOOKUP[21]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXFD_PF_LOOKUP_SHFT 21
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXBF_STA_VLD_ADDR   WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXBF_STA_VLD_MASK   0x00100000                // CR_MAN_TXBF_STA_VLD[20]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXBF_STA_VLD_SHFT   20
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXBF_STA_ADDR       WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXBF_STA_MASK       0x000C0000                // CR_MAN_TXBF_STA[19..18]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_MAN_TXBF_STA_SHFT       18
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_BFER_FORCE_ANGLE_EN_ADDR WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_BFER_FORCE_ANGLE_EN_MASK 0x00020000                // CR_BF_BFER_FORCE_ANGLE_EN[17]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_BFER_FORCE_ANGLE_EN_SHFT 17
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_BFEE_FORCE_ANGLE_EN_ADDR WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_BFEE_FORCE_ANGLE_EN_MASK 0x00010000                // CR_BF_BFEE_FORCE_ANGLE_EN[16]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_BFEE_FORCE_ANGLE_EN_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFTX_ROLLBACK_ENB_ADDR  WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFTX_ROLLBACK_ENB_MASK  0x00008000                // CR_BFTX_ROLLBACK_ENB[15]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFTX_ROLLBACK_ENB_SHFT  15
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFOFF_ENB_2BF2SS_ADDR   WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFOFF_ENB_2BF2SS_MASK   0x00004000                // CR_BFOFF_ENB_2BF2SS[14]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFOFF_ENB_2BF2SS_SHFT   14
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFOFF_ENB_3BF3SS_ADDR   WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFOFF_ENB_3BF3SS_MASK   0x00002000                // CR_BFOFF_ENB_3BF3SS[13]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BFOFF_ENB_3BF3SS_SHFT   13
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_PFMU_SWAP_SEG_EN_ADDR   WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_PFMU_SWAP_SEG_EN_MASK   0x00000100                // CR_PFMU_SWAP_SEG_EN[8]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_PFMU_SWAP_SEG_EN_SHFT   8
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_DBDC_BAND_SEL_ADDR   WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_DBDC_BAND_SEL_MASK   0x00000010                // CR_BF_DBDC_BAND_SEL[4]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BF_DBDC_BAND_SEL_SHFT   4
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND1_RX_IBF_EN_ADDR    WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND1_RX_IBF_EN_MASK    0x00000008                // CR_BAND1_RX_IBF_EN[3]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND1_RX_IBF_EN_SHFT    3
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND1_RX_EBF_EN_ADDR    WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND1_RX_EBF_EN_MASK    0x00000004                // CR_BAND1_RX_EBF_EN[2]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND1_RX_EBF_EN_SHFT    2
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND0_RX_IBF_EN_ADDR    WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND0_RX_IBF_EN_MASK    0x00000002                // CR_BAND0_RX_IBF_EN[1]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND0_RX_IBF_EN_SHFT    1
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND0_RX_EBF_EN_ADDR    WF_PHYRX_CTRL_CR_BF_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND0_RX_EBF_EN_MASK    0x00000001                // CR_BAND0_RX_EBF_EN[0]
#define WF_PHYRX_CTRL_CR_BF_CONTROL_CR_BAND0_RX_EBF_EN_SHFT    0

/* =====================================================================================

  ---CR_BF_PFILE_ACCESS (0x82000000 + 0x4804)---

    CR_BF_PFILE_SCIDX[9..0]      - (RW) [DE] PFMU subcarrier index selection, signed 10-bit format.
    CR_BF_PFILE_PFID_SEL[19..10] - (RW) [DE] PFMU Profile ID selection, from 0~1023.
    CR_BF_PFILE_TAG_SEL[21..20]  - (RW) [DE] PFMU Tag selection.
                                     0: select Data
                                     1: select Tag1
                                     2: select Tag2
                                     3: select PN
    CR_BF_PFILE_PN_SEL[24..22]   - (RW) [DE] PFMU power normalization factor selection.
                                     0: select PN for DBW20
                                     1: select PN for DBW40
                                     2: select PN for DBW80
                                     3: select PN for DBW160NC
    RESERVED25[25]               - (RO) Reserved bits
    CR_BF_PFILE_SEL[27..26]      - (RW) [DE] PFMU profile selection.
                                     0: select eBFee RAM
                                     1: select PFMU RAM, including Data and Control units
                                     2. select Temperary Buffer RAM
                                     3: select TxBF Qd RAM
    RESERVED28[29..28]           - (RO) Reserved bits
    CR_BF_PFILE_RD_TRIG[30]      - (RW) [DE] Trigger PFMU profile read.
    CR_BF_PFILE_WR_TRIG[31]      - (RW) [DE] Trigger PFMU profile write.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_WR_TRIG_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_WR_TRIG_MASK 0x80000000                // CR_BF_PFILE_WR_TRIG[31]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_WR_TRIG_SHFT 31
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_RD_TRIG_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_RD_TRIG_MASK 0x40000000                // CR_BF_PFILE_RD_TRIG[30]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_RD_TRIG_SHFT 30
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_SEL_ADDR  WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_SEL_MASK  0x0C000000                // CR_BF_PFILE_SEL[27..26]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_SEL_SHFT  26
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_PN_SEL_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_PN_SEL_MASK 0x01C00000                // CR_BF_PFILE_PN_SEL[24..22]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_PN_SEL_SHFT 22
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_TAG_SEL_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_TAG_SEL_MASK 0x00300000                // CR_BF_PFILE_TAG_SEL[21..20]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_TAG_SEL_SHFT 20
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_PFID_SEL_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_PFID_SEL_MASK 0x000FFC00                // CR_BF_PFILE_PFID_SEL[19..10]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_PFID_SEL_SHFT 10
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_SCIDX_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_SCIDX_MASK 0x000003FF                // CR_BF_PFILE_SCIDX[9..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_ACCESS_CR_BF_PFILE_SCIDX_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_0 (0x82000000 + 0x4808)---

    CR_BF_PFILE_WDATA0[31..0]    - (RW) [DE] PFMU write data part-0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_0_CR_BF_PFILE_WDATA0_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_0_CR_BF_PFILE_WDATA0_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA0[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_0_CR_BF_PFILE_WDATA0_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_1 (0x82000000 + 0x480C)---

    CR_BF_PFILE_WDATA1[31..0]    - (RW) [DE] PFMU write data part-1

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_1_CR_BF_PFILE_WDATA1_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_1_CR_BF_PFILE_WDATA1_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA1[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_1_CR_BF_PFILE_WDATA1_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_2 (0x82000000 + 0x4810)---

    CR_BF_PFILE_WDATA2[31..0]    - (RW) [DE] PFMU write data part-2

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_2_CR_BF_PFILE_WDATA2_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_2_CR_BF_PFILE_WDATA2_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA2[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_2_CR_BF_PFILE_WDATA2_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_3 (0x82000000 + 0x4814)---

    CR_BF_PFILE_WDATA3[31..0]    - (RW) [DE] PFMU write data part-3

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_3_CR_BF_PFILE_WDATA3_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_3_CR_BF_PFILE_WDATA3_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA3[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_3_CR_BF_PFILE_WDATA3_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_4 (0x82000000 + 0x4818)---

    CR_BF_PFILE_WDATA4[31..0]    - (RW) [DE] PFMU write data part-4

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_4_CR_BF_PFILE_WDATA4_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_4_CR_BF_PFILE_WDATA4_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA4[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_4_CR_BF_PFILE_WDATA4_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_5 (0x82000000 + 0x481C)---

    CR_BF_PFILE_WDATA5[31..0]    - (RW) [DE] PFMU write data part-5

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_5_CR_BF_PFILE_WDATA5_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_5_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_5_CR_BF_PFILE_WDATA5_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA5[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_5_CR_BF_PFILE_WDATA5_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_0 (0x82000000 + 0x4820)---

    RO_BF_PFILE_RDATA0[31..0]    - (RO) [DE] PFMU read data part-0

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_0_RO_BF_PFILE_RDATA0_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_0_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_0_RO_BF_PFILE_RDATA0_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA0[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_0_RO_BF_PFILE_RDATA0_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_1 (0x82000000 + 0x4824)---

    RO_BF_PFILE_RDATA1[31..0]    - (RO) [DE] PFMU read data part-1

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_1_RO_BF_PFILE_RDATA1_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_1_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_1_RO_BF_PFILE_RDATA1_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA1[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_1_RO_BF_PFILE_RDATA1_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_2 (0x82000000 + 0x4828)---

    RO_BF_PFILE_RDATA2[31..0]    - (RO) [DE] PFMU read data part-2

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_2_RO_BF_PFILE_RDATA2_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_2_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_2_RO_BF_PFILE_RDATA2_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA2[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_2_RO_BF_PFILE_RDATA2_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_3 (0x82000000 + 0x482C)---

    RO_BF_PFILE_RDATA3[31..0]    - (RO) [DE] PFMU read data part-3

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_3_RO_BF_PFILE_RDATA3_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_3_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_3_RO_BF_PFILE_RDATA3_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA3[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_3_RO_BF_PFILE_RDATA3_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_4 (0x82000000 + 0x4830)---

    RO_BF_PFILE_RDATA4[31..0]    - (RO) [DE] PFMU read data part-4

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_4_RO_BF_PFILE_RDATA4_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_4_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_4_RO_BF_PFILE_RDATA4_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA4[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_4_RO_BF_PFILE_RDATA4_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_5 (0x82000000 + 0x4834)---

    RO_BF_PFILE_RDATA5[31..0]    - (RO) [DE] PFMU read data part-5

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_5_RO_BF_PFILE_RDATA5_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_5_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_5_RO_BF_PFILE_RDATA5_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA5[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_5_RO_BF_PFILE_RDATA5_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_6 (0x82000000 + 0x4838)---

    RO_BF_PFILE_RDATA6[31..0]    - (RO) [DE] PFMU read data part-6

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_6_RO_BF_PFILE_RDATA6_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_6_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_6_RO_BF_PFILE_RDATA6_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA6[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_6_RO_BF_PFILE_RDATA6_SHFT 0

/* =====================================================================================

  ---CR_BF_PFMU_CONTROL (0x82000000 + 0x483C)---

    CR_IBF_FAST_TIMER[0]         - (RW) [DE] For RTL simulation only. Do not touch!
    CR_IBF_PATIAL_UPD_ENB[1]     - (RW) Obsolete.
    CR_IBF_UPD_CHK_BP[2]         - (RW) [CSD] Bypass all checks when iBF profile update.
    CR_IBF_UPD_SM_ANT_CHK_BP[3]  - (RW) [CSD] Bypass smart antenna config. check when iBF profile update.
    CR_IBF_UPD_DBW_CHK_BP[4]     - (RW) [DE] Bypass desired DBW check when iBF profile update.
    CR_IBF_UPD_NR_CHK_BP[5]      - (RW) [DE] Bypass desired Nr check when iBF profile update.
    CR_IBF_UPD_NC_CHK_BP[6]      - (RW) [DE] Bypass desired Nc check when iBF profile update.
    CR_MAN_BFEE_RDY_ENB[7]       - (RW) [DE] Manual value for phy3mac_bfee_rdy.
    CR_MAN_BFEE_RDY[8]           - (RW) [DE] Manual control phy2mac_bfee_rdy.
    CR_AUTOCLR_BFEE_RDY_ENB[9]   - (RW) [DE] Auto-clear phy2mac_bfee_rdy when mac2phy_bfee_sound_n de-asserts
    CR_IBF_UPD_RU_CHK_BP[10]     - (RW) [DE] Bypass desired RU check when iBF profile update. (For HE packets' use.)
    RESERVED11[31..11]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_RU_CHK_BP_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_RU_CHK_BP_MASK 0x00000400                // CR_IBF_UPD_RU_CHK_BP[10]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_RU_CHK_BP_SHFT 10
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_AUTOCLR_BFEE_RDY_ENB_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_AUTOCLR_BFEE_RDY_ENB_MASK 0x00000200                // CR_AUTOCLR_BFEE_RDY_ENB[9]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_AUTOCLR_BFEE_RDY_ENB_SHFT 9
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_MAN_BFEE_RDY_ADDR  WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_MAN_BFEE_RDY_MASK  0x00000100                // CR_MAN_BFEE_RDY[8]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_MAN_BFEE_RDY_SHFT  8
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_MAN_BFEE_RDY_ENB_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_MAN_BFEE_RDY_ENB_MASK 0x00000080                // CR_MAN_BFEE_RDY_ENB[7]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_MAN_BFEE_RDY_ENB_SHFT 7
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_NC_CHK_BP_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_NC_CHK_BP_MASK 0x00000040                // CR_IBF_UPD_NC_CHK_BP[6]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_NC_CHK_BP_SHFT 6
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_NR_CHK_BP_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_NR_CHK_BP_MASK 0x00000020                // CR_IBF_UPD_NR_CHK_BP[5]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_NR_CHK_BP_SHFT 5
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_DBW_CHK_BP_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_DBW_CHK_BP_MASK 0x00000010                // CR_IBF_UPD_DBW_CHK_BP[4]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_DBW_CHK_BP_SHFT 4
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_SM_ANT_CHK_BP_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_SM_ANT_CHK_BP_MASK 0x00000008                // CR_IBF_UPD_SM_ANT_CHK_BP[3]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_SM_ANT_CHK_BP_SHFT 3
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_CHK_BP_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_CHK_BP_MASK 0x00000004                // CR_IBF_UPD_CHK_BP[2]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_UPD_CHK_BP_SHFT 2
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_PATIAL_UPD_ENB_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_PATIAL_UPD_ENB_MASK 0x00000002                // CR_IBF_PATIAL_UPD_ENB[1]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_PATIAL_UPD_ENB_SHFT 1
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_FAST_TIMER_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_FAST_TIMER_MASK 0x00000001                // CR_IBF_FAST_TIMER[0]
#define WF_PHYRX_CTRL_CR_BF_PFMU_CONTROL_CR_IBF_FAST_TIMER_SHFT 0

/* =====================================================================================

  ---CR_BF_PFMU_DBG (0x82000000 + 0x4840)---

    CR_BF_DBG_SEL[2..0]          - (RW) [DE] PFMU debug bus selection.
    RESERVED3[3]                 - (RO) Reserved bits
    CR_BF_FBK_PAD_OPTION[4]      - (RW) [DE] BFer data padding option for feedback data by BFee. (For those codebook options of psi/phi < 7/9 bits)
                                     0: pad all 0s to LSB
                                     1: pad {1 bit 1 then all 0s} to LSB
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_CR_BF_FBK_PAD_OPTION_ADDR WF_PHYRX_CTRL_CR_BF_PFMU_DBG_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_CR_BF_FBK_PAD_OPTION_MASK 0x00000010                // CR_BF_FBK_PAD_OPTION[4]
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_CR_BF_FBK_PAD_OPTION_SHFT 4
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_CR_BF_DBG_SEL_ADDR        WF_PHYRX_CTRL_CR_BF_PFMU_DBG_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_CR_BF_DBG_SEL_MASK        0x00000007                // CR_BF_DBG_SEL[2..0]
#define WF_PHYRX_CTRL_CR_BF_PFMU_DBG_CR_BF_DBG_SEL_SHFT        0

/* =====================================================================================

  ---RO_BF_STATUS (0x82000000 + 0x4844)---

    RO_BF_STATUS[31..0]          - (RO) [DE] PFMU status bus.

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_STATUS_RO_BF_STATUS_ADDR           WF_PHYRX_CTRL_RO_BF_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_BF_STATUS_RO_BF_STATUS_MASK           0xFFFFFFFF                // RO_BF_STATUS[31..0]
#define WF_PHYRX_CTRL_RO_BF_STATUS_RO_BF_STATUS_SHFT           0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_0 (0x82000000 + 0x4848)---

    CR_BF_FORCE_ANGLE0[31..0]    - (RW) [CSD] Angle value part-0 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_0_CR_BF_FORCE_ANGLE0_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_0_CR_BF_FORCE_ANGLE0_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE0[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_0_CR_BF_FORCE_ANGLE0_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_1 (0x82000000 + 0x484C)---

    CR_BF_FORCE_ANGLE1[31..0]    - (RW) [CSD] Angle value part-1 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_1_CR_BF_FORCE_ANGLE1_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_1_CR_BF_FORCE_ANGLE1_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE1[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_1_CR_BF_FORCE_ANGLE1_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_2 (0x82000000 + 0x4850)---

    CR_BF_FORCE_ANGLE2[31..0]    - (RW) [CSD] Angle value part-2 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_2_CR_BF_FORCE_ANGLE2_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_2_CR_BF_FORCE_ANGLE2_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE2[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_2_CR_BF_FORCE_ANGLE2_SHFT 0

/* =====================================================================================

  ---CR_BF_MAN_RXBF_CONTROL_0 (0x82000000 + 0x4854)---

    CR_MAN_RXBF_PFID[9..0]       - (RW) [DE] Manual value for mac2phy_rxbf_pfid.
    RESERVED10[22..10]           - (RO) Reserved bits
    CR_MAN_RXBF_STA[24..23]      - (RW) [DE] Manual value for mac2phy_rxbf_sta.
    RESERVED25[29..25]           - (RO) Reserved bits
    CR_MAN_RXBF_STA_VLD_TRIG[30] - (RW) [DE] Manual trigger mac2phy_rxbf_sta_vld.
    CR_MAN_RXBF_STA_EN[31]       - (RW) [DE] Manual control mac2phy_rxbf_* related signals.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_EN_ADDR WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_EN_MASK 0x80000000                // CR_MAN_RXBF_STA_EN[31]
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_EN_SHFT 31
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_VLD_TRIG_ADDR WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_VLD_TRIG_MASK 0x40000000                // CR_MAN_RXBF_STA_VLD_TRIG[30]
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_VLD_TRIG_SHFT 30
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_ADDR WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_MASK 0x01800000                // CR_MAN_RXBF_STA[24..23]
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_STA_SHFT 23
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_PFID_ADDR WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_PFID_MASK 0x000003FF                // CR_MAN_RXBF_PFID[9..0]
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_0_CR_MAN_RXBF_PFID_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_0 (0x82000000 + 0x4858)---

    CR_PN_METHOD_RX_IBF[0]       - (RW) [CSD] PN method select for SU (rx iBF)
                                     1'b0: uniform
                                     1'b1: max_total
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_0_CR_PN_METHOD_RX_IBF_ADDR     WF_PHYRX_CTRL_CR_BF_SVD_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_0_CR_PN_METHOD_RX_IBF_MASK     0x00000001                // CR_PN_METHOD_RX_IBF[0]
#define WF_PHYRX_CTRL_CR_BF_SVD_0_CR_PN_METHOD_RX_IBF_SHFT     0

/* =====================================================================================

  ---CR_BF_SVD_1 (0x82000000 + 0x485C)---

    CR_SVD_DROP_RX_IDX[1..0]     - (RW) [CSD] SVD drop RX index
                                     2'b00: drop rx 0
                                     2'b01: drop rx 1
                                     2'b10: drop rx 2
                                     2'b11: drop rx 3
    RESERVED2[3..2]              - (RO) Reserved bits
    CR_CMPRS_EBFEE_CSD_RM_EN[4]  - (RW) [CSD] Compression CSD remove enable
                                     1'b0: disable
                                     1'b1: enable
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_1_CR_CMPRS_EBFEE_CSD_RM_EN_ADDR WF_PHYRX_CTRL_CR_BF_SVD_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_1_CR_CMPRS_EBFEE_CSD_RM_EN_MASK 0x00000010                // CR_CMPRS_EBFEE_CSD_RM_EN[4]
#define WF_PHYRX_CTRL_CR_BF_SVD_1_CR_CMPRS_EBFEE_CSD_RM_EN_SHFT 4
#define WF_PHYRX_CTRL_CR_BF_SVD_1_CR_SVD_DROP_RX_IDX_ADDR      WF_PHYRX_CTRL_CR_BF_SVD_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_1_CR_SVD_DROP_RX_IDX_MASK      0x00000003                // CR_SVD_DROP_RX_IDX[1..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_1_CR_SVD_DROP_RX_IDX_SHFT      0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER0_0 (0x82000000 + 0x4860)---

    RO_MI_BPSK_OUT_USER0[6..0]   - (RO) Metric report BPSK for User0
    RESERVED7[7]                 - (RO) Reserved bits
    RO_MI_QPSK_OUT_USER0[14..8]  - (RO) Metric report QPSK for User0
    RESERVED15[15]               - (RO) Reserved bits
    RO_MI_16QAM_OUT_USER0[22..16] - (RO) Metric report 16QAM for User0
    RESERVED23[23]               - (RO) Reserved bits
    RO_MI_64QAM_OUT_USER0[30..24] - (RO) Metric report 64QAM for User0
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_64QAM_OUT_USER0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_64QAM_OUT_USER0_MASK 0x7F000000                // RO_MI_64QAM_OUT_USER0[30..24]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_64QAM_OUT_USER0_SHFT 24
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_16QAM_OUT_USER0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_16QAM_OUT_USER0_MASK 0x007F0000                // RO_MI_16QAM_OUT_USER0[22..16]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_16QAM_OUT_USER0_SHFT 16
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_QPSK_OUT_USER0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_QPSK_OUT_USER0_MASK 0x00007F00                // RO_MI_QPSK_OUT_USER0[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_QPSK_OUT_USER0_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_BPSK_OUT_USER0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_BPSK_OUT_USER0_MASK 0x0000007F                // RO_MI_BPSK_OUT_USER0[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_0_RO_MI_BPSK_OUT_USER0_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER0_1 (0x82000000 + 0x4864)---

    RO_MI_256QAM_OUT_USER0[6..0] - (RO) Metric report 256QAM for User0
    RESERVED7[7]                 - (RO) Reserved bits
    RO_CAPACITY_OUT_USER0[14..8] - (RO) Metric report capacity for User0
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_RO_CAPACITY_OUT_USER0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_RO_CAPACITY_OUT_USER0_MASK 0x00007F00                // RO_CAPACITY_OUT_USER0[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_RO_CAPACITY_OUT_USER0_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_RO_MI_256QAM_OUT_USER0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_RO_MI_256QAM_OUT_USER0_MASK 0x0000007F                // RO_MI_256QAM_OUT_USER0[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER0_1_RO_MI_256QAM_OUT_USER0_SHFT 0

/* =====================================================================================

  ---RO_MUTX_TX_ERR_PATTERN_0 (0x82000000 + 0x4868)---

    RO_MUTX_TX_ERR_PATTERN0[31..0] - (RO) [DE] Error report field-0 when TxBF is not correctly applied.

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_0_RO_MUTX_TX_ERR_PATTERN0_ADDR WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_0_RO_MUTX_TX_ERR_PATTERN0_MASK 0xFFFFFFFF                // RO_MUTX_TX_ERR_PATTERN0[31..0]
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_0_RO_MUTX_TX_ERR_PATTERN0_SHFT 0

/* =====================================================================================

  ---RO_MUTX_TX_ERR_PATTERN_1 (0x82000000 + 0x486C)---

    RO_MUTX_TX_ERR_PATTERN1[31..0] - (RO) [DE] Error report field-1 when TxBF is not correctly applied.

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_1_RO_MUTX_TX_ERR_PATTERN1_ADDR WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_1_RO_MUTX_TX_ERR_PATTERN1_MASK 0xFFFFFFFF                // RO_MUTX_TX_ERR_PATTERN1[31..0]
#define WF_PHYRX_CTRL_RO_MUTX_TX_ERR_PATTERN_1_RO_MUTX_TX_ERR_PATTERN1_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_ERR_PATTERN_0 (0x82000000 + 0x4870)---

    RO_MUTX_LQ_ERR_PATTERN0[31..0] - (RO) [DE] Error report field-0 when LQ is not correctly initiated.

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_0_RO_MUTX_LQ_ERR_PATTERN0_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_0_RO_MUTX_LQ_ERR_PATTERN0_MASK 0xFFFFFFFF                // RO_MUTX_LQ_ERR_PATTERN0[31..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_0_RO_MUTX_LQ_ERR_PATTERN0_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_ERR_PATTERN_1 (0x82000000 + 0x4874)---

    RO_MUTX_LQ_ERR_PATTERN1[31..0] - (RO) [DE] Error report field-1 when LQ is not correctly initiated.

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_1_RO_MUTX_LQ_ERR_PATTERN1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_1_RO_MUTX_LQ_ERR_PATTERN1_MASK 0xFFFFFFFF                // RO_MUTX_LQ_ERR_PATTERN1[31..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_ERR_PATTERN_1_RO_MUTX_LQ_ERR_PATTERN1_SHFT 0

/* =====================================================================================

  ---RO_MUTX_STATUS (0x82000000 + 0x4878)---

    RO_MUTX_STATUS[31..0]        - (RO) [DE] MUTX status bus.

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_STATUS_RO_MUTX_STATUS_ADDR       WF_PHYRX_CTRL_RO_MUTX_STATUS_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_STATUS_RO_MUTX_STATUS_MASK       0xFFFFFFFF                // RO_MUTX_STATUS[31..0]
#define WF_PHYRX_CTRL_RO_MUTX_STATUS_RO_MUTX_STATUS_SHFT       0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER1_0 (0x82000000 + 0x487C)---

    RO_MI_BPSK_OUT_USER1[6..0]   - (RO) Metric report BPSK for User1
    RESERVED7[7]                 - (RO) Reserved bits
    RO_MI_QPSK_OUT_USER1[14..8]  - (RO) Metric report QPSK for User1
    RESERVED15[15]               - (RO) Reserved bits
    RO_MI_16QAM_OUT_USER1[22..16] - (RO) Metric report 16QAM for User1
    RESERVED23[23]               - (RO) Reserved bits
    RO_MI_64QAM_OUT_USER1[30..24] - (RO) Metric report 64QAM for User1
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_64QAM_OUT_USER1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_64QAM_OUT_USER1_MASK 0x7F000000                // RO_MI_64QAM_OUT_USER1[30..24]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_64QAM_OUT_USER1_SHFT 24
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_16QAM_OUT_USER1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_16QAM_OUT_USER1_MASK 0x007F0000                // RO_MI_16QAM_OUT_USER1[22..16]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_16QAM_OUT_USER1_SHFT 16
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_QPSK_OUT_USER1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_QPSK_OUT_USER1_MASK 0x00007F00                // RO_MI_QPSK_OUT_USER1[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_QPSK_OUT_USER1_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_BPSK_OUT_USER1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_BPSK_OUT_USER1_MASK 0x0000007F                // RO_MI_BPSK_OUT_USER1[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_0_RO_MI_BPSK_OUT_USER1_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER1_1 (0x82000000 + 0x4880)---

    RO_MI_256QAM_OUT_USER1[6..0] - (RO) Metric report 256QAM for User1
    RESERVED7[7]                 - (RO) Reserved bits
    RO_CAPACITY_OUT_USER1[14..8] - (RO) Metric report capacity for User1
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_RO_CAPACITY_OUT_USER1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_RO_CAPACITY_OUT_USER1_MASK 0x00007F00                // RO_CAPACITY_OUT_USER1[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_RO_CAPACITY_OUT_USER1_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_RO_MI_256QAM_OUT_USER1_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_RO_MI_256QAM_OUT_USER1_MASK 0x0000007F                // RO_MI_256QAM_OUT_USER1[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER1_1_RO_MI_256QAM_OUT_USER1_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER2_0 (0x82000000 + 0x4884)---

    RO_MI_BPSK_OUT_USER2[6..0]   - (RO) Metric report BPSK for User2
    RESERVED7[7]                 - (RO) Reserved bits
    RO_MI_QPSK_OUT_USER2[14..8]  - (RO) Metric report QPSK for User2
    RESERVED15[15]               - (RO) Reserved bits
    RO_MI_16QAM_OUT_USER2[22..16] - (RO) Metric report 16QAM for User2
    RESERVED23[23]               - (RO) Reserved bits
    RO_MI_64QAM_OUT_USER2[30..24] - (RO) Metric report 64QAM for User2
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_64QAM_OUT_USER2_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_64QAM_OUT_USER2_MASK 0x7F000000                // RO_MI_64QAM_OUT_USER2[30..24]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_64QAM_OUT_USER2_SHFT 24
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_16QAM_OUT_USER2_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_16QAM_OUT_USER2_MASK 0x007F0000                // RO_MI_16QAM_OUT_USER2[22..16]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_16QAM_OUT_USER2_SHFT 16
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_QPSK_OUT_USER2_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_QPSK_OUT_USER2_MASK 0x00007F00                // RO_MI_QPSK_OUT_USER2[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_QPSK_OUT_USER2_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_BPSK_OUT_USER2_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_BPSK_OUT_USER2_MASK 0x0000007F                // RO_MI_BPSK_OUT_USER2[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_0_RO_MI_BPSK_OUT_USER2_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER2_1 (0x82000000 + 0x4888)---

    RO_MI_256QAM_OUT_USER2[6..0] - (RO) Metric report 256QAM for User2
    RESERVED7[7]                 - (RO) Reserved bits
    RO_CAPACITY_OUT_USER2[14..8] - (RO) Metric report capacity for User2
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_RO_CAPACITY_OUT_USER2_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_RO_CAPACITY_OUT_USER2_MASK 0x00007F00                // RO_CAPACITY_OUT_USER2[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_RO_CAPACITY_OUT_USER2_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_RO_MI_256QAM_OUT_USER2_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_RO_MI_256QAM_OUT_USER2_MASK 0x0000007F                // RO_MI_256QAM_OUT_USER2[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER2_1_RO_MI_256QAM_OUT_USER2_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER3_0 (0x82000000 + 0x488C)---

    RO_MI_BPSK_OUT_USER3[6..0]   - (RO) Metric report BPSK for User3
    RESERVED7[7]                 - (RO) Reserved bits
    RO_MI_QPSK_OUT_USER3[14..8]  - (RO) Metric report QPSK for User3
    RESERVED15[15]               - (RO) Reserved bits
    RO_MI_16QAM_OUT_USER3[22..16] - (RO) Metric report 16QAM for User3
    RESERVED23[23]               - (RO) Reserved bits
    RO_MI_64QAM_OUT_USER3[30..24] - (RO) Metric report 64QAM for User3
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_64QAM_OUT_USER3_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_64QAM_OUT_USER3_MASK 0x7F000000                // RO_MI_64QAM_OUT_USER3[30..24]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_64QAM_OUT_USER3_SHFT 24
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_16QAM_OUT_USER3_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_16QAM_OUT_USER3_MASK 0x007F0000                // RO_MI_16QAM_OUT_USER3[22..16]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_16QAM_OUT_USER3_SHFT 16
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_QPSK_OUT_USER3_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_QPSK_OUT_USER3_MASK 0x00007F00                // RO_MI_QPSK_OUT_USER3[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_QPSK_OUT_USER3_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_BPSK_OUT_USER3_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_BPSK_OUT_USER3_MASK 0x0000007F                // RO_MI_BPSK_OUT_USER3[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_0_RO_MI_BPSK_OUT_USER3_SHFT 0

/* =====================================================================================

  ---RO_MUTX_LQ_RPT_USER3_1 (0x82000000 + 0x4890)---

    RO_MI_256QAM_OUT_USER3[6..0] - (RO) Metric report 256QAM for User3
    RESERVED7[7]                 - (RO) Reserved bits
    RO_CAPACITY_OUT_USER3[14..8] - (RO) Metric report capacity for User3
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_RO_CAPACITY_OUT_USER3_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_RO_CAPACITY_OUT_USER3_MASK 0x00007F00                // RO_CAPACITY_OUT_USER3[14..8]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_RO_CAPACITY_OUT_USER3_SHFT 8
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_RO_MI_256QAM_OUT_USER3_ADDR WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_ADDR
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_RO_MI_256QAM_OUT_USER3_MASK 0x0000007F                // RO_MI_256QAM_OUT_USER3[6..0]
#define WF_PHYRX_CTRL_RO_MUTX_LQ_RPT_USER3_1_RO_MI_256QAM_OUT_USER3_SHFT 0

/* =====================================================================================

  ---CR_BF_SHIFT_SNR_0 (0x82000000 + 0x489C)---

    CR_BF_BW_SNR_OFFSET_BW40[4..0] - (RW) [CSD] BF BW SNR offset for BW40 in s4.0
    RESERVED5[7..5]              - (RO) Reserved bits
    CR_BF_BW_SNR_OFFSET_BW80[12..8] - (RW) [CSD] BF BW SNR offset for BW80 in s4.0
    RESERVED13[15..13]           - (RO) Reserved bits
    CR_BF_BW_SNR_OFFSET_BW160C[20..16] - (RW) [CSD] BF BW SNR offset for BW160C in s4.0
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_BF_BW_SNR_OFFSET_BW160NC[28..24] - (RW) [CSD] BF BW SNR offset for BW160NC in s4.0
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW160NC_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW160NC_MASK 0x1F000000                // CR_BF_BW_SNR_OFFSET_BW160NC[28..24]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW160NC_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW160C_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW160C_MASK 0x001F0000                // CR_BF_BW_SNR_OFFSET_BW160C[20..16]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW160C_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW80_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW80_MASK 0x00001F00                // CR_BF_BW_SNR_OFFSET_BW80[12..8]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW80_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW40_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW40_MASK 0x0000001F                // CR_BF_BW_SNR_OFFSET_BW40[4..0]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_0_CR_BF_BW_SNR_OFFSET_BW40_SHFT 0

/* =====================================================================================

  ---CR_BF_SHIFT_SNR_1 (0x82000000 + 0x48A0)---

    CR_EBFEE_AVGSNR_FOR_UNSUP_NRNC[7..0] - (RW) [CSD]  If Nr/Nc > BFEE max supported dimension, feedback CR_EBFEE_PHI/PSI/AVGSNR/DSNR_FOR_UNSUP_NRNC.
    RESERVED8[15..8]             - (RO) Reserved bits
    CR_MUTX_SE_IN_CSD_SC_IDX_ROLLBACK[16] - (RW) [DE] Rollback option of the modification for MT7622 phase jump in BW20 CSD 25ns issue
    RESERVED17[19..17]           - (RO) Reserved bits
    CR_BF_RSSI_SHIFT_SNR_ENB[20] - (RW) [CSD] BF RSSI shift SNR enable
    RESERVED21[23..21]           - (RO) Reserved bits
    CR_BF_BW_SNR_OFFSET_BW20[28..24] - (RW) [CSD] BF BW SNR offset for BW160NC in s4.0
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_BF_BW_SNR_OFFSET_BW20_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_BF_BW_SNR_OFFSET_BW20_MASK 0x1F000000                // CR_BF_BW_SNR_OFFSET_BW20[28..24]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_BF_BW_SNR_OFFSET_BW20_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_BF_RSSI_SHIFT_SNR_ENB_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_BF_RSSI_SHIFT_SNR_ENB_MASK 0x00100000                // CR_BF_RSSI_SHIFT_SNR_ENB[20]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_BF_RSSI_SHIFT_SNR_ENB_SHFT 20
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_MUTX_SE_IN_CSD_SC_IDX_ROLLBACK_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_MUTX_SE_IN_CSD_SC_IDX_ROLLBACK_MASK 0x00010000                // CR_MUTX_SE_IN_CSD_SC_IDX_ROLLBACK[16]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_MUTX_SE_IN_CSD_SC_IDX_ROLLBACK_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_EBFEE_AVGSNR_FOR_UNSUP_NRNC_ADDR WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_EBFEE_AVGSNR_FOR_UNSUP_NRNC_MASK 0x000000FF                // CR_EBFEE_AVGSNR_FOR_UNSUP_NRNC[7..0]
#define WF_PHYRX_CTRL_CR_BF_SHIFT_SNR_1_CR_EBFEE_AVGSNR_FOR_UNSUP_NRNC_SHFT 0

/* =====================================================================================

  ---CR_BF_IBF_IRQ_STATUS_0 (0x82000000 + 0x48A4)---

    RESERVED0[29..0]             - (RO) Reserved bits
    CR_IBF_CLR_PF_RENEW_STATUS_PLS[30] - (RW) [DE] A pulse to clear RO_PFMU_IBF_TIMER_RENEW_STATUS_0/1.
    CR_IBF_CLR_PF_EXPIRE_STATUS_PLS[31] - (RW) [DE] A pulse to clear RO_PFMU_IBF_TIMER_EXPIRE_STATUS_0/1.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_CR_IBF_CLR_PF_EXPIRE_STATUS_PLS_ADDR WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_CR_IBF_CLR_PF_EXPIRE_STATUS_PLS_MASK 0x80000000                // CR_IBF_CLR_PF_EXPIRE_STATUS_PLS[31]
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_CR_IBF_CLR_PF_EXPIRE_STATUS_PLS_SHFT 31
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_CR_IBF_CLR_PF_RENEW_STATUS_PLS_ADDR WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_CR_IBF_CLR_PF_RENEW_STATUS_PLS_MASK 0x40000000                // CR_IBF_CLR_PF_RENEW_STATUS_PLS[30]
#define WF_PHYRX_CTRL_CR_BF_IBF_IRQ_STATUS_0_CR_IBF_CLR_PF_RENEW_STATUS_PLS_SHFT 30

/* =====================================================================================

  ---RO_BF_IBF_EXPIRE_STATUS_0 (0x82000000 + 0x48A8)---

    RO_PFMU_IBF_TIMER_EXPIRE_STATUS_0[31..0] - (RO) [DE] PFMU iBF timer expire status for PFID[31:0].

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_0_RO_PFMU_IBF_TIMER_EXPIRE_STATUS_0_ADDR WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_0_ADDR
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_0_RO_PFMU_IBF_TIMER_EXPIRE_STATUS_0_MASK 0xFFFFFFFF                // RO_PFMU_IBF_TIMER_EXPIRE_STATUS_0[31..0]
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_0_RO_PFMU_IBF_TIMER_EXPIRE_STATUS_0_SHFT 0

/* =====================================================================================

  ---RO_BF_IBF_EXPIRE_STATUS_1 (0x82000000 + 0x48AC)---

    RO_PFMU_IBF_TIMER_EXPIRE_STATUS_1[31..0] - (RO) [DE] PFMU iBF timer expire status for PFID[63:32].

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_1_RO_PFMU_IBF_TIMER_EXPIRE_STATUS_1_ADDR WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_1_ADDR
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_1_RO_PFMU_IBF_TIMER_EXPIRE_STATUS_1_MASK 0xFFFFFFFF                // RO_PFMU_IBF_TIMER_EXPIRE_STATUS_1[31..0]
#define WF_PHYRX_CTRL_RO_BF_IBF_EXPIRE_STATUS_1_RO_PFMU_IBF_TIMER_EXPIRE_STATUS_1_SHFT 0

/* =====================================================================================

  ---RO_BF_IBF_RENEW_STATUS_0 (0x82000000 + 0x48B0)---

    RO_PFMU_IBF_TIMER_RENEW_STATUS_0[31..0] - (RO) [DE] PFMU iBF timer renew status for PFID[31:0].

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_0_RO_PFMU_IBF_TIMER_RENEW_STATUS_0_ADDR WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_0_ADDR
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_0_RO_PFMU_IBF_TIMER_RENEW_STATUS_0_MASK 0xFFFFFFFF                // RO_PFMU_IBF_TIMER_RENEW_STATUS_0[31..0]
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_0_RO_PFMU_IBF_TIMER_RENEW_STATUS_0_SHFT 0

/* =====================================================================================

  ---RO_BF_IBF_RENEW_STATUS_1 (0x82000000 + 0x48B4)---

    RO_PFMU_IBF_TIMER_RENEW_STATUS_1[31..0] - (RO) [DE] PFMU iBF timer renew status for PFID[63:32].

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_1_RO_PFMU_IBF_TIMER_RENEW_STATUS_1_ADDR WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_1_ADDR
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_1_RO_PFMU_IBF_TIMER_RENEW_STATUS_1_MASK 0xFFFFFFFF                // RO_PFMU_IBF_TIMER_RENEW_STATUS_1[31..0]
#define WF_PHYRX_CTRL_RO_BF_IBF_RENEW_STATUS_1_RO_PFMU_IBF_TIMER_RENEW_STATUS_1_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_3 (0x82000000 + 0x48B8)---

    CR_BF_FORCE_ANGLE3[31..0]    - (RW) [CSD] Angle value part-3 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_3_CR_BF_FORCE_ANGLE3_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_3_CR_BF_FORCE_ANGLE3_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE3[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_3_CR_BF_FORCE_ANGLE3_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_4 (0x82000000 + 0x48BC)---

    CR_BF_FORCE_ANGLE4[31..0]    - (RW) [CSD] Angle value part-4 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_4_CR_BF_FORCE_ANGLE4_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_4_CR_BF_FORCE_ANGLE4_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE4[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_4_CR_BF_FORCE_ANGLE4_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_5 (0x82000000 + 0x48C0)---

    CR_BF_FORCE_ANGLE5[31..0]    - (RW) [CSD] Angle value part-5 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_5_CR_BF_FORCE_ANGLE5_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_5_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_5_CR_BF_FORCE_ANGLE5_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE5[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_5_CR_BF_FORCE_ANGLE5_SHFT 0

/* =====================================================================================

  ---CR_BF_BFEE_BLOCK_SVD_WR (0x82000000 + 0x48C8)---

    CR_EBFEE_PHI_FOR_UNSUP_NRNC[8..0] - (RW) [CSD]  If Nr/Nc > BFEE max supported dimension, feedback CR_EBFEE_PHI/PSI/AVGSNR/DSNR_FOR_UNSUP_NRNC.
    CR_EBFEE_PSI_FOR_UNSUP_NRNC[15..9] - (RW) [CSD]  If Nr/Nc > BFEE max supported dimension, feedback CR_EBFEE_PHI/PSI/AVGSNR/DSNR_FOR_UNSUP_NRNC.
    CR_EBFEE_DSNR_FOR_UNSUP_NRNC[19..16] - (RW) [CSD]  If Nr/Nc > BFEE max supported dimension, feedback CR_EBFEE_PHI/PSI/AVGSNR/DSNR_FOR_UNSUP_NRNC.
    RESERVED20[23..20]           - (RO) Reserved bits
    CR_EBFEE_MAX_NC_SUPPORTED[26..24] - (RW) [CSD] BFEE max supported dimension. If Nr > this dimension, feedback CR_EBFEE_PHI/PSI/AVGSNR/DSNR_FOR_UNSUP_NRNC.
    CR_EBFEE_MAX_NR_SUPPORTED[29..27] - (RW) [CSD] BFEE max supported dimension. If Nr > this dimension, feedback CR_EBFEE_PHI/PSI/AVGSNR/DSNR_FOR_UNSUP_NRNC.
    CR_EBFEE_DSNR_USE_MEM_ONLY[30] - (RW) [CSD] BFEE dSNR use RAM value only. Do not substract AVG SNR.  (for manual mode usage)
    CR_BF_BFEE_BLOCK_SVD_WR[31]  - (RW) [CSD] Disable SVD writing Bfee angle and dSNR RAM (for manual mode usage)

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_BF_BFEE_BLOCK_SVD_WR_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_BF_BFEE_BLOCK_SVD_WR_MASK 0x80000000                // CR_BF_BFEE_BLOCK_SVD_WR[31]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_BF_BFEE_BLOCK_SVD_WR_SHFT 31
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_DSNR_USE_MEM_ONLY_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_DSNR_USE_MEM_ONLY_MASK 0x40000000                // CR_EBFEE_DSNR_USE_MEM_ONLY[30]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_DSNR_USE_MEM_ONLY_SHFT 30
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_MAX_NR_SUPPORTED_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_MAX_NR_SUPPORTED_MASK 0x38000000                // CR_EBFEE_MAX_NR_SUPPORTED[29..27]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_MAX_NR_SUPPORTED_SHFT 27
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_MAX_NC_SUPPORTED_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_MAX_NC_SUPPORTED_MASK 0x07000000                // CR_EBFEE_MAX_NC_SUPPORTED[26..24]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_MAX_NC_SUPPORTED_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_DSNR_FOR_UNSUP_NRNC_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_DSNR_FOR_UNSUP_NRNC_MASK 0x000F0000                // CR_EBFEE_DSNR_FOR_UNSUP_NRNC[19..16]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_DSNR_FOR_UNSUP_NRNC_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_PSI_FOR_UNSUP_NRNC_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_PSI_FOR_UNSUP_NRNC_MASK 0x0000FE00                // CR_EBFEE_PSI_FOR_UNSUP_NRNC[15..9]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_PSI_FOR_UNSUP_NRNC_SHFT 9
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_PHI_FOR_UNSUP_NRNC_ADDR WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_ADDR
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_PHI_FOR_UNSUP_NRNC_MASK 0x000001FF                // CR_EBFEE_PHI_FOR_UNSUP_NRNC[8..0]
#define WF_PHYRX_CTRL_CR_BF_BFEE_BLOCK_SVD_WR_CR_EBFEE_PHI_FOR_UNSUP_NRNC_SHFT 0

/* =====================================================================================

  ---CR_EBFEE_TAG_AVG_SNR0 (0x82000000 + 0x48CC)---

    CR_EBFEE_TAG_AVG_SNR_STS2[7..0] - (RW) [CSD] BFEE reported AVG SNRs for STS2 at manual mode.
    CR_EBFEE_TAG_AVG_SNR_STS1[15..8] - (RW) [CSD] BFEE reported AVG SNRs for STS1 at manual mode.
    CR_EBFEE_TAG_AVG_SNR_STS0[23..16] - (RW) [CSD] BFEE reported AVG SNRs for STS0 at manual mode.
    RESERVED24[30..24]           - (RO) Reserved bits
    CR_EBFEE_TAG_AVG_SNR_MAN[31] - (RW) [CSD] BFEE reported AVG SNRs use manual mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_MAN_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_MAN_MASK 0x80000000                // CR_EBFEE_TAG_AVG_SNR_MAN[31]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_MAN_SHFT 31
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS0_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS0_MASK 0x00FF0000                // CR_EBFEE_TAG_AVG_SNR_STS0[23..16]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS0_SHFT 16
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS1_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS1_MASK 0x0000FF00                // CR_EBFEE_TAG_AVG_SNR_STS1[15..8]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS1_SHFT 8
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS2_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS2_MASK 0x000000FF                // CR_EBFEE_TAG_AVG_SNR_STS2[7..0]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR0_CR_EBFEE_TAG_AVG_SNR_STS2_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_6 (0x82000000 + 0x48D0)---

    CR_BF_FORCE_ANGLE6[31..0]    - (RW) [CSD] Angle value part-6 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_6_CR_BF_FORCE_ANGLE6_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_6_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_6_CR_BF_FORCE_ANGLE6_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE6[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_6_CR_BF_FORCE_ANGLE6_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_7 (0x82000000 + 0x48D4)---

    CR_BF_FORCE_ANGLE7[31..0]    - (RW) [CSD] Angle value part-7 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_7_CR_BF_FORCE_ANGLE7_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_7_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_7_CR_BF_FORCE_ANGLE7_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE7[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_7_CR_BF_FORCE_ANGLE7_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_8 (0x82000000 + 0x48D8)---

    CR_BF_FORCE_ANGLE8[31..0]    - (RW) [CSD] Angle value part-8 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_8_CR_BF_FORCE_ANGLE8_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_8_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_8_CR_BF_FORCE_ANGLE8_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE8[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_8_CR_BF_FORCE_ANGLE8_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_9 (0x82000000 + 0x48DC)---

    CR_BF_FORCE_ANGLE9[31..0]    - (RW) [CSD] Angle value part-9 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_9_CR_BF_FORCE_ANGLE9_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_9_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_9_CR_BF_FORCE_ANGLE9_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE9[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_9_CR_BF_FORCE_ANGLE9_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_10 (0x82000000 + 0x48E0)---

    CR_BF_FORCE_ANGLE10[31..0]   - (RW) [CSD] Angle value part-10 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_10_CR_BF_FORCE_ANGLE10_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_10_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_10_CR_BF_FORCE_ANGLE10_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE10[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_10_CR_BF_FORCE_ANGLE10_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_11 (0x82000000 + 0x48E4)---

    CR_BF_FORCE_ANGLE11[31..0]   - (RW) [CSD] Angle value part-11 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_11_CR_BF_FORCE_ANGLE11_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_11_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_11_CR_BF_FORCE_ANGLE11_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE11[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_11_CR_BF_FORCE_ANGLE11_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_12 (0x82000000 + 0x48E8)---

    CR_BF_FORCE_ANGLE12[31..0]   - (RW) [CSD] Angle value part-12 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_12_CR_BF_FORCE_ANGLE12_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_12_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_12_CR_BF_FORCE_ANGLE12_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE12[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_12_CR_BF_FORCE_ANGLE12_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_13 (0x82000000 + 0x48EC)---

    CR_BF_FORCE_ANGLE13[31..0]   - (RW) [CSD] Angle value part-13 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_13_CR_BF_FORCE_ANGLE13_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_13_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_13_CR_BF_FORCE_ANGLE13_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE13[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_13_CR_BF_FORCE_ANGLE13_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_14 (0x82000000 + 0x48F0)---

    CR_BF_FORCE_ANGLE14[31..0]   - (RW) [CSD] Angle value part-14 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_14_CR_BF_FORCE_ANGLE14_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_14_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_14_CR_BF_FORCE_ANGLE14_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE14[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_14_CR_BF_FORCE_ANGLE14_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_15 (0x82000000 + 0x48F4)---

    CR_BF_FORCE_ANGLE15[31..0]   - (RW) [CSD] Angle value part-15 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_15_CR_BF_FORCE_ANGLE15_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_15_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_15_CR_BF_FORCE_ANGLE15_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE15[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_15_CR_BF_FORCE_ANGLE15_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_16 (0x82000000 + 0x48F8)---

    CR_BF_FORCE_ANGLE16[31..0]   - (RW) [CSD] Angle value part-16 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_16_CR_BF_FORCE_ANGLE16_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_16_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_16_CR_BF_FORCE_ANGLE16_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE16[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_16_CR_BF_FORCE_ANGLE16_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_17 (0x82000000 + 0x48FC)---

    CR_BF_FORCE_ANGLE17[31..0]   - (RW) [CSD] Angle value part-17 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_17_CR_BF_FORCE_ANGLE17_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_17_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_17_CR_BF_FORCE_ANGLE17_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE17[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_17_CR_BF_FORCE_ANGLE17_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_18 (0x82000000 + 0x4900)---

    CR_BF_FORCE_ANGLE18[31..0]   - (RW) [CSD] Angle value part-18 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_18_CR_BF_FORCE_ANGLE18_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_18_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_18_CR_BF_FORCE_ANGLE18_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE18[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_18_CR_BF_FORCE_ANGLE18_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_19 (0x82000000 + 0x4904)---

    CR_BF_FORCE_ANGLE19[31..0]   - (RW) [CSD] Angle value part-19 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_19_CR_BF_FORCE_ANGLE19_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_19_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_19_CR_BF_FORCE_ANGLE19_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE19[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_19_CR_BF_FORCE_ANGLE19_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_20 (0x82000000 + 0x4908)---

    CR_BF_FORCE_ANGLE20[31..0]   - (RW) [CSD] Angle value part-20 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_20_CR_BF_FORCE_ANGLE20_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_20_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_20_CR_BF_FORCE_ANGLE20_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE20[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_20_CR_BF_FORCE_ANGLE20_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_21 (0x82000000 + 0x490C)---

    CR_BF_FORCE_ANGLE21[31..0]   - (RW) [CSD] Angle value part-21 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_21_CR_BF_FORCE_ANGLE21_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_21_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_21_CR_BF_FORCE_ANGLE21_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE21[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_21_CR_BF_FORCE_ANGLE21_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_22 (0x82000000 + 0x4910)---

    CR_BF_FORCE_ANGLE22[31..0]   - (RW) [CSD] Angle value part-22 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_22_CR_BF_FORCE_ANGLE22_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_22_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_22_CR_BF_FORCE_ANGLE22_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE22[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_22_CR_BF_FORCE_ANGLE22_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_23 (0x82000000 + 0x4914)---

    CR_BF_FORCE_ANGLE23[31..0]   - (RW) [CSD] Angle value part-23 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_23_CR_BF_FORCE_ANGLE23_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_23_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_23_CR_BF_FORCE_ANGLE23_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE23[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_23_CR_BF_FORCE_ANGLE23_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_24 (0x82000000 + 0x4918)---

    CR_BF_FORCE_ANGLE24[31..0]   - (RW) [CSD] Angle value part-24 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_24_CR_BF_FORCE_ANGLE24_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_24_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_24_CR_BF_FORCE_ANGLE24_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE24[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_24_CR_BF_FORCE_ANGLE24_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_25 (0x82000000 + 0x491C)---

    CR_BF_FORCE_ANGLE25[31..0]   - (RW) [CSD] Angle value part-25 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_25_CR_BF_FORCE_ANGLE25_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_25_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_25_CR_BF_FORCE_ANGLE25_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE25[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_25_CR_BF_FORCE_ANGLE25_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_26 (0x82000000 + 0x4920)---

    CR_BF_FORCE_ANGLE26[31..0]   - (RW) [CSD] Angle value part-26 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_26_CR_BF_FORCE_ANGLE26_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_26_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_26_CR_BF_FORCE_ANGLE26_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE26[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_26_CR_BF_FORCE_ANGLE26_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_ANGLE_27 (0x82000000 + 0x4924)---

    CR_BF_FORCE_ANGLE27[31..0]   - (RW) [CSD] Angle value part-27 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_27_CR_BF_FORCE_ANGLE27_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_27_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_27_CR_BF_FORCE_ANGLE27_MASK 0xFFFFFFFF                // CR_BF_FORCE_ANGLE27[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_ANGLE_27_CR_BF_FORCE_ANGLE27_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_DSNR_0 (0x82000000 + 0x4928)---

    CR_BF_FORCE_DSNR0[31..0]     - (RW) [CSD] DSNR value part-0 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_0_CR_BF_FORCE_DSNR0_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_0_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_0_CR_BF_FORCE_DSNR0_MASK 0xFFFFFFFF                // CR_BF_FORCE_DSNR0[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_0_CR_BF_FORCE_DSNR0_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_DSNR_1 (0x82000000 + 0x492C)---

    CR_BF_FORCE_DSNR1[31..0]     - (RW) [CSD] DSNR value part-1 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_1_CR_BF_FORCE_DSNR1_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_1_CR_BF_FORCE_DSNR1_MASK 0xFFFFFFFF                // CR_BF_FORCE_DSNR1[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_1_CR_BF_FORCE_DSNR1_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_DSNR_2 (0x82000000 + 0x4930)---

    CR_BF_FORCE_DSNR2[31..0]     - (RW) [CSD] DSNR value part-2 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_2_CR_BF_FORCE_DSNR2_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_2_CR_BF_FORCE_DSNR2_MASK 0xFFFFFFFF                // CR_BF_FORCE_DSNR2[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_2_CR_BF_FORCE_DSNR2_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_DSNR_3 (0x82000000 + 0x4934)---

    CR_BF_FORCE_DSNR3[31..0]     - (RW) [CSD] DSNR value part-3 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_3_CR_BF_FORCE_DSNR3_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_3_CR_BF_FORCE_DSNR3_MASK 0xFFFFFFFF                // CR_BF_FORCE_DSNR3[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_3_CR_BF_FORCE_DSNR3_SHFT 0

/* =====================================================================================

  ---CR_BF_FORCE_DSNR_4 (0x82000000 + 0x4938)---

    CR_BF_FORCE_DSNR4[31..0]     - (RW) [CSD] DSNR value part-4 for PFMU force mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_4_CR_BF_FORCE_DSNR4_ADDR WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_4_CR_BF_FORCE_DSNR4_MASK 0xFFFFFFFF                // CR_BF_FORCE_DSNR4[31..0]
#define WF_PHYRX_CTRL_CR_BF_FORCE_DSNR_4_CR_BF_FORCE_DSNR4_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_7 (0x82000000 + 0x493C)---

    RO_BF_PFILE_RDATA7[31..0]    - (RO) [DE] PFMU read data part-7

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_7_RO_BF_PFILE_RDATA7_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_7_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_7_RO_BF_PFILE_RDATA7_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA7[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_7_RO_BF_PFILE_RDATA7_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_8 (0x82000000 + 0x4940)---

    RO_BF_PFILE_RDATA8[31..0]    - (RO) [DE] PFMU read data part-8

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_8_RO_BF_PFILE_RDATA8_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_8_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_8_RO_BF_PFILE_RDATA8_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA8[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_8_RO_BF_PFILE_RDATA8_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_9 (0x82000000 + 0x4944)---

    RO_BF_PFILE_RDATA9[31..0]    - (RO) [DE] PFMU read data part-9

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_9_RO_BF_PFILE_RDATA9_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_9_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_9_RO_BF_PFILE_RDATA9_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA9[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_9_RO_BF_PFILE_RDATA9_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_10 (0x82000000 + 0x4948)---

    RO_BF_PFILE_RDATA10[31..0]   - (RO) [DE] PFMU read data part-10

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_10_RO_BF_PFILE_RDATA10_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_10_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_10_RO_BF_PFILE_RDATA10_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA10[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_10_RO_BF_PFILE_RDATA10_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_11 (0x82000000 + 0x494C)---

    RO_BF_PFILE_RDATA11[31..0]   - (RO) [DE] PFMU read data part-11

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_11_RO_BF_PFILE_RDATA11_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_11_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_11_RO_BF_PFILE_RDATA11_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA11[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_11_RO_BF_PFILE_RDATA11_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_12 (0x82000000 + 0x4950)---

    RO_BF_PFILE_RDATA12[31..0]   - (RO) [DE] PFMU read data part-12

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_12_RO_BF_PFILE_RDATA12_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_12_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_12_RO_BF_PFILE_RDATA12_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA12[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_12_RO_BF_PFILE_RDATA12_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_13 (0x82000000 + 0x4954)---

    RO_BF_PFILE_RDATA13[31..0]   - (RO) [DE] PFMU read data part-13

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_13_RO_BF_PFILE_RDATA13_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_13_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_13_RO_BF_PFILE_RDATA13_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA13[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_13_RO_BF_PFILE_RDATA13_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_14 (0x82000000 + 0x4958)---

    RO_BF_PFILE_RDATA14[31..0]   - (RO) [DE] PFMU read data part-14

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_14_RO_BF_PFILE_RDATA14_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_14_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_14_RO_BF_PFILE_RDATA14_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA14[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_14_RO_BF_PFILE_RDATA14_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_15 (0x82000000 + 0x495C)---

    RO_BF_PFILE_RDATA15[31..0]   - (RO) [DE] PFMU read data part-15

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_15_RO_BF_PFILE_RDATA15_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_15_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_15_RO_BF_PFILE_RDATA15_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA15[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_15_RO_BF_PFILE_RDATA15_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_16 (0x82000000 + 0x4960)---

    RO_BF_PFILE_RDATA16[31..0]   - (RO) [DE] PFMU read data part-16

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_16_RO_BF_PFILE_RDATA16_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_16_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_16_RO_BF_PFILE_RDATA16_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA16[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_16_RO_BF_PFILE_RDATA16_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_17 (0x82000000 + 0x4964)---

    RO_BF_PFILE_RDATA17[31..0]   - (RO) [DE] PFMU read data part-17

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_17_RO_BF_PFILE_RDATA17_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_17_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_17_RO_BF_PFILE_RDATA17_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA17[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_17_RO_BF_PFILE_RDATA17_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_18 (0x82000000 + 0x4968)---

    RO_BF_PFILE_RDATA18[31..0]   - (RO) [DE] PFMU read data part-18

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_18_RO_BF_PFILE_RDATA18_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_18_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_18_RO_BF_PFILE_RDATA18_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA18[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_18_RO_BF_PFILE_RDATA18_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_19 (0x82000000 + 0x496C)---

    RO_BF_PFILE_RDATA19[31..0]   - (RO) [DE] PFMU read data part-19

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_19_RO_BF_PFILE_RDATA19_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_19_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_19_RO_BF_PFILE_RDATA19_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA19[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_19_RO_BF_PFILE_RDATA19_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_20 (0x82000000 + 0x4970)---

    RO_BF_PFILE_RDATA20[31..0]   - (RO) [DE] PFMU read data part-20

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_20_RO_BF_PFILE_RDATA20_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_20_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_20_RO_BF_PFILE_RDATA20_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA20[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_20_RO_BF_PFILE_RDATA20_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_21 (0x82000000 + 0x4974)---

    RO_BF_PFILE_RDATA21[31..0]   - (RO) [DE] PFMU read data part-21

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_21_RO_BF_PFILE_RDATA21_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_21_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_21_RO_BF_PFILE_RDATA21_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA21[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_21_RO_BF_PFILE_RDATA21_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_22 (0x82000000 + 0x4978)---

    RO_BF_PFILE_RDATA22[31..0]   - (RO) [DE] PFMU read data part-22

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_22_RO_BF_PFILE_RDATA22_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_22_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_22_RO_BF_PFILE_RDATA22_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA22[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_22_RO_BF_PFILE_RDATA22_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_23 (0x82000000 + 0x497C)---

    RO_BF_PFILE_RDATA23[31..0]   - (RO) [DE] PFMU read data part-23

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_23_RO_BF_PFILE_RDATA23_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_23_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_23_RO_BF_PFILE_RDATA23_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA23[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_23_RO_BF_PFILE_RDATA23_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_24 (0x82000000 + 0x4980)---

    RO_BF_PFILE_RDATA24[31..0]   - (RO) [DE] PFMU read data part-24

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_24_RO_BF_PFILE_RDATA24_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_24_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_24_RO_BF_PFILE_RDATA24_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA24[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_24_RO_BF_PFILE_RDATA24_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_25 (0x82000000 + 0x4984)---

    RO_BF_PFILE_RDATA25[31..0]   - (RO) [DE] PFMU read data part-25

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_25_RO_BF_PFILE_RDATA25_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_25_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_25_RO_BF_PFILE_RDATA25_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA25[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_25_RO_BF_PFILE_RDATA25_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_26 (0x82000000 + 0x4988)---

    RO_BF_PFILE_RDATA26[31..0]   - (RO) [DE] PFMU read data part-26

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_26_RO_BF_PFILE_RDATA26_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_26_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_26_RO_BF_PFILE_RDATA26_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA26[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_26_RO_BF_PFILE_RDATA26_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_27 (0x82000000 + 0x498C)---

    RO_BF_PFILE_RDATA27[31..0]   - (RO) [DE] PFMU read data part-27

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_27_RO_BF_PFILE_RDATA27_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_27_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_27_RO_BF_PFILE_RDATA27_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA27[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_27_RO_BF_PFILE_RDATA27_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_28 (0x82000000 + 0x4990)---

    RO_BF_PFILE_RDATA28[31..0]   - (RO) [DE] PFMU read data part-28

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_28_RO_BF_PFILE_RDATA28_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_28_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_28_RO_BF_PFILE_RDATA28_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA28[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_28_RO_BF_PFILE_RDATA28_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_29 (0x82000000 + 0x4994)---

    RO_BF_PFILE_RDATA29[31..0]   - (RO) [DE] PFMU read data part-29

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_29_RO_BF_PFILE_RDATA29_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_29_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_29_RO_BF_PFILE_RDATA29_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA29[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_29_RO_BF_PFILE_RDATA29_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_30 (0x82000000 + 0x4998)---

    RO_BF_PFILE_RDATA30[31..0]   - (RO) [DE] PFMU read data part-30

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_30_RO_BF_PFILE_RDATA30_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_30_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_30_RO_BF_PFILE_RDATA30_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA30[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_30_RO_BF_PFILE_RDATA30_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_31 (0x82000000 + 0x499C)---

    RO_BF_PFILE_RDATA31[31..0]   - (RO) [DE] PFMU read data part-31

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_31_RO_BF_PFILE_RDATA31_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_31_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_31_RO_BF_PFILE_RDATA31_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA31[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_31_RO_BF_PFILE_RDATA31_SHFT 0

/* =====================================================================================

  ---RO_BF_PFILE_RDATA_32 (0x82000000 + 0x49A0)---

    RO_BF_PFILE_RDATA32[31..0]   - (RO) [DE] PFMU read data part-32

 =====================================================================================*/
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_32_RO_BF_PFILE_RDATA32_ADDR WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_32_ADDR
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_32_RO_BF_PFILE_RDATA32_MASK 0xFFFFFFFF                // RO_BF_PFILE_RDATA32[31..0]
#define WF_PHYRX_CTRL_RO_BF_PFILE_RDATA_32_RO_BF_PFILE_RDATA32_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_6 (0x82000000 + 0x49A4)---

    CR_BF_PFILE_WDATA6[31..0]    - (RW) [DE] PFMU write data part-6

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_6_CR_BF_PFILE_WDATA6_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_6_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_6_CR_BF_PFILE_WDATA6_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA6[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_6_CR_BF_PFILE_WDATA6_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_7 (0x82000000 + 0x49A8)---

    CR_BF_PFILE_WDATA7[31..0]    - (RW) [DE] PFMU write data part-7

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_7_CR_BF_PFILE_WDATA7_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_7_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_7_CR_BF_PFILE_WDATA7_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA7[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_7_CR_BF_PFILE_WDATA7_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_8 (0x82000000 + 0x49AC)---

    CR_BF_PFILE_WDATA8[31..0]    - (RW) [DE] PFMU write data part-8

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_8_CR_BF_PFILE_WDATA8_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_8_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_8_CR_BF_PFILE_WDATA8_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA8[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_8_CR_BF_PFILE_WDATA8_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_9 (0x82000000 + 0x49B0)---

    CR_BF_PFILE_WDATA9[31..0]    - (RW) [DE] PFMU write data part-9

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_9_CR_BF_PFILE_WDATA9_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_9_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_9_CR_BF_PFILE_WDATA9_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA9[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_9_CR_BF_PFILE_WDATA9_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_10 (0x82000000 + 0x49B4)---

    CR_BF_PFILE_WDATA10[31..0]   - (RW) [DE] PFMU write data part-10

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_10_CR_BF_PFILE_WDATA10_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_10_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_10_CR_BF_PFILE_WDATA10_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA10[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_10_CR_BF_PFILE_WDATA10_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_11 (0x82000000 + 0x49B8)---

    CR_BF_PFILE_WDATA11[31..0]   - (RW) [DE] PFMU write data part-11

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_11_CR_BF_PFILE_WDATA11_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_11_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_11_CR_BF_PFILE_WDATA11_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA11[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_11_CR_BF_PFILE_WDATA11_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_12 (0x82000000 + 0x49BC)---

    CR_BF_PFILE_WDATA12[31..0]   - (RW) [DE] PFMU write data part-12

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_12_CR_BF_PFILE_WDATA12_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_12_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_12_CR_BF_PFILE_WDATA12_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA12[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_12_CR_BF_PFILE_WDATA12_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_13 (0x82000000 + 0x49C0)---

    CR_BF_PFILE_WDATA13[31..0]   - (RW) [DE] PFMU write data part-13

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_13_CR_BF_PFILE_WDATA13_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_13_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_13_CR_BF_PFILE_WDATA13_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA13[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_13_CR_BF_PFILE_WDATA13_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_14 (0x82000000 + 0x49C4)---

    CR_BF_PFILE_WDATA14[31..0]   - (RW) [DE] PFMU write data part-14

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_14_CR_BF_PFILE_WDATA14_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_14_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_14_CR_BF_PFILE_WDATA14_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA14[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_14_CR_BF_PFILE_WDATA14_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_15 (0x82000000 + 0x49C8)---

    CR_BF_PFILE_WDATA15[31..0]   - (RW) [DE] PFMU write data part-15

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_15_CR_BF_PFILE_WDATA15_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_15_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_15_CR_BF_PFILE_WDATA15_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA15[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_15_CR_BF_PFILE_WDATA15_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_16 (0x82000000 + 0x49CC)---

    CR_BF_PFILE_WDATA16[31..0]   - (RW) [DE] PFMU write data part-16

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_16_CR_BF_PFILE_WDATA16_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_16_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_16_CR_BF_PFILE_WDATA16_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA16[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_16_CR_BF_PFILE_WDATA16_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_17 (0x82000000 + 0x49D0)---

    CR_BF_PFILE_WDATA17[31..0]   - (RW) [DE] PFMU write data part-17

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_17_CR_BF_PFILE_WDATA17_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_17_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_17_CR_BF_PFILE_WDATA17_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA17[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_17_CR_BF_PFILE_WDATA17_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_18 (0x82000000 + 0x49D4)---

    CR_BF_PFILE_WDATA18[31..0]   - (RW) [DE] PFMU write data part-18

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_18_CR_BF_PFILE_WDATA18_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_18_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_18_CR_BF_PFILE_WDATA18_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA18[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_18_CR_BF_PFILE_WDATA18_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_19 (0x82000000 + 0x49D8)---

    CR_BF_PFILE_WDATA19[31..0]   - (RW) [DE] PFMU write data part-19

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_19_CR_BF_PFILE_WDATA19_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_19_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_19_CR_BF_PFILE_WDATA19_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA19[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_19_CR_BF_PFILE_WDATA19_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_20 (0x82000000 + 0x49DC)---

    CR_BF_PFILE_WDATA20[31..0]   - (RW) [DE] PFMU write data part-20

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_20_CR_BF_PFILE_WDATA20_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_20_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_20_CR_BF_PFILE_WDATA20_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA20[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_20_CR_BF_PFILE_WDATA20_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_21 (0x82000000 + 0x49E0)---

    CR_BF_PFILE_WDATA21[31..0]   - (RW) [DE] PFMU write data part-21

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_21_CR_BF_PFILE_WDATA21_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_21_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_21_CR_BF_PFILE_WDATA21_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA21[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_21_CR_BF_PFILE_WDATA21_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_22 (0x82000000 + 0x49E4)---

    CR_BF_PFILE_WDATA22[31..0]   - (RW) [DE] PFMU write data part-22

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_22_CR_BF_PFILE_WDATA22_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_22_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_22_CR_BF_PFILE_WDATA22_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA22[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_22_CR_BF_PFILE_WDATA22_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_23 (0x82000000 + 0x49E8)---

    CR_BF_PFILE_WDATA23[31..0]   - (RW) [DE] PFMU write data part-23

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_23_CR_BF_PFILE_WDATA23_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_23_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_23_CR_BF_PFILE_WDATA23_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA23[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_23_CR_BF_PFILE_WDATA23_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_24 (0x82000000 + 0x49EC)---

    CR_BF_PFILE_WDATA24[31..0]   - (RW) [DE] PFMU write data part-24

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_24_CR_BF_PFILE_WDATA24_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_24_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_24_CR_BF_PFILE_WDATA24_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA24[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_24_CR_BF_PFILE_WDATA24_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_25 (0x82000000 + 0x49F0)---

    CR_BF_PFILE_WDATA25[31..0]   - (RW) [DE] PFMU write data part-25

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_25_CR_BF_PFILE_WDATA25_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_25_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_25_CR_BF_PFILE_WDATA25_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA25[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_25_CR_BF_PFILE_WDATA25_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_26 (0x82000000 + 0x49F4)---

    CR_BF_PFILE_WDATA26[31..0]   - (RW) [DE] PFMU write data part-26

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_26_CR_BF_PFILE_WDATA26_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_26_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_26_CR_BF_PFILE_WDATA26_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA26[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_26_CR_BF_PFILE_WDATA26_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_27 (0x82000000 + 0x49F8)---

    CR_BF_PFILE_WDATA27[31..0]   - (RW) [DE] PFMU write data part-27

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_27_CR_BF_PFILE_WDATA27_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_27_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_27_CR_BF_PFILE_WDATA27_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA27[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_27_CR_BF_PFILE_WDATA27_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_28 (0x82000000 + 0x49FC)---

    CR_BF_PFILE_WDATA28[31..0]   - (RW) [DE] PFMU write data part-28

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_28_CR_BF_PFILE_WDATA28_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_28_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_28_CR_BF_PFILE_WDATA28_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA28[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_28_CR_BF_PFILE_WDATA28_SHFT 0

/* =====================================================================================

  ---CR_BF_PFILE_WDATA_29 (0x82000000 + 0x4A00)---

    CR_BF_PFILE_WDATA29[31..0]   - (RW) [DE] PFMU write data part-29

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_29_CR_BF_PFILE_WDATA29_ADDR WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_29_ADDR
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_29_CR_BF_PFILE_WDATA29_MASK 0xFFFFFFFF                // CR_BF_PFILE_WDATA29[31..0]
#define WF_PHYRX_CTRL_CR_BF_PFILE_WDATA_29_CR_BF_PFILE_WDATA29_SHFT 0

/* =====================================================================================

  ---CR_EBFEE_TAG_AVG_SNR1 (0x82000000 + 0x4A04)---

    CR_EBFEE_TAG_AVG_SNR_STS6[7..0] - (RW) [CSD] BFEE reported AVG SNRs for STS6 at manual mode.
    CR_EBFEE_TAG_AVG_SNR_STS5[15..8] - (RW) [CSD] BFEE reported AVG SNRs for STS5 at manual mode.
    CR_EBFEE_TAG_AVG_SNR_STS4[23..16] - (RW) [CSD] BFEE reported AVG SNRs for STS4 at manual mode.
    CR_EBFEE_TAG_AVG_SNR_STS3[31..24] - (RW) [CSD] BFEE reported AVG SNRs for STS3 at manual mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS3_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS3_MASK 0xFF000000                // CR_EBFEE_TAG_AVG_SNR_STS3[31..24]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS3_SHFT 24
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS4_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS4_MASK 0x00FF0000                // CR_EBFEE_TAG_AVG_SNR_STS4[23..16]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS4_SHFT 16
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS5_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS5_MASK 0x0000FF00                // CR_EBFEE_TAG_AVG_SNR_STS5[15..8]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS5_SHFT 8
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS6_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS6_MASK 0x000000FF                // CR_EBFEE_TAG_AVG_SNR_STS6[7..0]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR1_CR_EBFEE_TAG_AVG_SNR_STS6_SHFT 0

/* =====================================================================================

  ---CR_EBFEE_TAG_AVG_SNR2 (0x82000000 + 0x4A08)---

    RESERVED0[23..0]             - (RO) Reserved bits
    CR_EBFEE_TAG_AVG_SNR_STS7[31..24] - (RW) [CSD] BFEE reported AVG SNRs for STS7 at manual mode.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR2_CR_EBFEE_TAG_AVG_SNR_STS7_ADDR WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR2_ADDR
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR2_CR_EBFEE_TAG_AVG_SNR_STS7_MASK 0xFF000000                // CR_EBFEE_TAG_AVG_SNR_STS7[31..24]
#define WF_PHYRX_CTRL_CR_EBFEE_TAG_AVG_SNR2_CR_EBFEE_TAG_AVG_SNR_STS7_SHFT 24

/* =====================================================================================

  ---CR_BF_MAN_RXBF_CONTROL_1 (0x82000000 + 0x4A0C)---

    CR_MAN_RXBF_ANT_ID[23..0]    - (RW) [DE] Manual value for mac2phy_rxbf_ant_id.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_1_CR_MAN_RXBF_ANT_ID_ADDR WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_1_ADDR
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_1_CR_MAN_RXBF_ANT_ID_MASK 0x00FFFFFF                // CR_MAN_RXBF_ANT_ID[23..0]
#define WF_PHYRX_CTRL_CR_BF_MAN_RXBF_CONTROL_1_CR_MAN_RXBF_ANT_ID_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_2 (0x82000000 + 0x4C00)---

    CR_RX_PHASE_COMP_VAL_HG_RX0[7..0] - (RW) [CSD] iBF compensation value for HG, RX0
    CR_RX_PHASE_COMP_VAL_HG_RX1[15..8] - (RW) [CSD] iBF compensation value for HG, RX1
    CR_RX_PHASE_COMP_VAL_HG_RX2[23..16] - (RW) [CSD] iBF compensation value for HG, RX2
    CR_RX_PHASE_COMP_VAL_HG_RX3[31..24] - (RW) [CSD] iBF compensation value for HG, RX3

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX3_ADDR WF_PHYRX_CTRL_CR_BF_SVD_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX3_MASK 0xFF000000                // CR_RX_PHASE_COMP_VAL_HG_RX3[31..24]
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX3_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX2_ADDR WF_PHYRX_CTRL_CR_BF_SVD_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX2_MASK 0x00FF0000                // CR_RX_PHASE_COMP_VAL_HG_RX2[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX2_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX1_ADDR WF_PHYRX_CTRL_CR_BF_SVD_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX1_MASK 0x0000FF00                // CR_RX_PHASE_COMP_VAL_HG_RX1[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX1_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX0_ADDR WF_PHYRX_CTRL_CR_BF_SVD_2_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX0_MASK 0x000000FF                // CR_RX_PHASE_COMP_VAL_HG_RX0[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_2_CR_RX_PHASE_COMP_VAL_HG_RX0_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_3 (0x82000000 + 0x4C04)---

    CR_RX_PHASE_COMP_VAL_MG_RX0[7..0] - (RW) [CSD] iBF compensation value for MG, RX0
    CR_RX_PHASE_COMP_VAL_MG_RX1[15..8] - (RW) [CSD] iBF compensation value for MG, RX1
    CR_RX_PHASE_COMP_VAL_MG_RX2[23..16] - (RW) [CSD] iBF compensation value for MG, RX2
    CR_RX_PHASE_COMP_VAL_MG_RX3[31..24] - (RW) [CSD] iBF compensation value for MG, RX3

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX3_ADDR WF_PHYRX_CTRL_CR_BF_SVD_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX3_MASK 0xFF000000                // CR_RX_PHASE_COMP_VAL_MG_RX3[31..24]
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX3_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX2_ADDR WF_PHYRX_CTRL_CR_BF_SVD_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX2_MASK 0x00FF0000                // CR_RX_PHASE_COMP_VAL_MG_RX2[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX2_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX1_ADDR WF_PHYRX_CTRL_CR_BF_SVD_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX1_MASK 0x0000FF00                // CR_RX_PHASE_COMP_VAL_MG_RX1[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX1_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX0_ADDR WF_PHYRX_CTRL_CR_BF_SVD_3_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX0_MASK 0x000000FF                // CR_RX_PHASE_COMP_VAL_MG_RX0[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_3_CR_RX_PHASE_COMP_VAL_MG_RX0_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_4 (0x82000000 + 0x4C08)---

    CR_RX_PHASE_COMP_VAL_LG_RX0[7..0] - (RW) [CSD] iBF compensation value for LG, RX0
    CR_RX_PHASE_COMP_VAL_LG_RX1[15..8] - (RW) [CSD] iBF compensation value for LG, RX1
    CR_RX_PHASE_COMP_VAL_LG_RX2[23..16] - (RW) [CSD] iBF compensation value for LG, RX2
    CR_RX_PHASE_COMP_VAL_LG_RX3[31..24] - (RW) [CSD] iBF compensation value for LG, RX3

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX3_ADDR WF_PHYRX_CTRL_CR_BF_SVD_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX3_MASK 0xFF000000                // CR_RX_PHASE_COMP_VAL_LG_RX3[31..24]
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX3_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX2_ADDR WF_PHYRX_CTRL_CR_BF_SVD_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX2_MASK 0x00FF0000                // CR_RX_PHASE_COMP_VAL_LG_RX2[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX2_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX1_ADDR WF_PHYRX_CTRL_CR_BF_SVD_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX1_MASK 0x0000FF00                // CR_RX_PHASE_COMP_VAL_LG_RX1[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX1_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX0_ADDR WF_PHYRX_CTRL_CR_BF_SVD_4_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX0_MASK 0x000000FF                // CR_RX_PHASE_COMP_VAL_LG_RX0[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_4_CR_RX_PHASE_COMP_VAL_LG_RX0_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_5 (0x82000000 + 0x4C0C)---

    CR_RES_PHASE_COMP_VAL_TX0[7..0] - (RW) [CSD] iBF compensation value for TX0
    CR_RES_PHASE_COMP_VAL_TX1[15..8] - (RW) [CSD] iBF compensation value for TX1
    CR_RES_PHASE_COMP_VAL_TX2[23..16] - (RW) [CSD] iBF compensation value for TX2
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX2_ADDR WF_PHYRX_CTRL_CR_BF_SVD_5_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX2_MASK 0x00FF0000                // CR_RES_PHASE_COMP_VAL_TX2[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX2_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX1_ADDR WF_PHYRX_CTRL_CR_BF_SVD_5_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX1_MASK 0x0000FF00                // CR_RES_PHASE_COMP_VAL_TX1[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX1_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX0_ADDR WF_PHYRX_CTRL_CR_BF_SVD_5_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX0_MASK 0x000000FF                // CR_RES_PHASE_COMP_VAL_TX0[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_5_CR_RES_PHASE_COMP_VAL_TX0_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_6 (0x82000000 + 0x4C10)---

    CR_RX_PHASE_COMP_VAL_UHG_RX0[7..0] - (RW) [CSD] iBF compensation value for UHG, RX0
    CR_RX_PHASE_COMP_VAL_UHG_RX1[15..8] - (RW) [CSD] iBF compensation value for UHG, RX1
    CR_RX_PHASE_COMP_VAL_UHG_RX2[23..16] - (RW) [CSD] iBF compensation value for UHG, RX2
    CR_RX_PHASE_COMP_VAL_UHG_RX3[31..24] - (RW) [CSD] iBF compensation value for UHG, RX3

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX3_ADDR WF_PHYRX_CTRL_CR_BF_SVD_6_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX3_MASK 0xFF000000                // CR_RX_PHASE_COMP_VAL_UHG_RX3[31..24]
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX3_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX2_ADDR WF_PHYRX_CTRL_CR_BF_SVD_6_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX2_MASK 0x00FF0000                // CR_RX_PHASE_COMP_VAL_UHG_RX2[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX2_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX1_ADDR WF_PHYRX_CTRL_CR_BF_SVD_6_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX1_MASK 0x0000FF00                // CR_RX_PHASE_COMP_VAL_UHG_RX1[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX1_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX0_ADDR WF_PHYRX_CTRL_CR_BF_SVD_6_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX0_MASK 0x000000FF                // CR_RX_PHASE_COMP_VAL_UHG_RX0[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_6_CR_RX_PHASE_COMP_VAL_UHG_RX0_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_7 (0x82000000 + 0x4C14)---

    CR_RX_PHASE_COMP_VAL_ULG_RX0[7..0] - (RW) [CSD] iBF compensation value for ULG, RX0
    CR_RX_PHASE_COMP_VAL_ULG_RX1[15..8] - (RW) [CSD] iBF compensation value for ULG, RX1
    CR_RX_PHASE_COMP_VAL_ULG_RX2[23..16] - (RW) [CSD] iBF compensation value for ULG, RX2
    CR_RX_PHASE_COMP_VAL_ULG_RX3[31..24] - (RW) [CSD] iBF compensation value for ULG, RX3

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX3_ADDR WF_PHYRX_CTRL_CR_BF_SVD_7_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX3_MASK 0xFF000000                // CR_RX_PHASE_COMP_VAL_ULG_RX3[31..24]
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX3_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX2_ADDR WF_PHYRX_CTRL_CR_BF_SVD_7_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX2_MASK 0x00FF0000                // CR_RX_PHASE_COMP_VAL_ULG_RX2[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX2_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX1_ADDR WF_PHYRX_CTRL_CR_BF_SVD_7_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX1_MASK 0x0000FF00                // CR_RX_PHASE_COMP_VAL_ULG_RX1[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX1_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX0_ADDR WF_PHYRX_CTRL_CR_BF_SVD_7_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX0_MASK 0x000000FF                // CR_RX_PHASE_COMP_VAL_ULG_RX0[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_7_CR_RX_PHASE_COMP_VAL_ULG_RX0_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_8 (0x82000000 + 0x4C18)---

    CR_RX_PHASE_COMP_VAL_LG_RX0_PRI[7..0] - (RO) [CSD] iBF compensation value for LG, RX0, primary segment
    CR_RX_PHASE_COMP_VAL_LG_RX1_PRI[15..8] - (RO) [CSD] iBF compensation value for LG, RX1, primary segment
    CR_RX_PHASE_COMP_VAL_LG_RX0_SEC[23..16] - (RO) [CSD] iBF compensation value for LG, RX0, secondary segment
    CR_RX_PHASE_COMP_VAL_LG_RX1_SEC[31..24] - (RO) [CSD] iBF compensation value for LG, RX1, secondary segment

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX1_SEC_ADDR WF_PHYRX_CTRL_CR_BF_SVD_8_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX1_SEC_MASK 0xFF000000                // CR_RX_PHASE_COMP_VAL_LG_RX1_SEC[31..24]
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX1_SEC_SHFT 24
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX0_SEC_ADDR WF_PHYRX_CTRL_CR_BF_SVD_8_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX0_SEC_MASK 0x00FF0000                // CR_RX_PHASE_COMP_VAL_LG_RX0_SEC[23..16]
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX0_SEC_SHFT 16
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX1_PRI_ADDR WF_PHYRX_CTRL_CR_BF_SVD_8_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX1_PRI_MASK 0x0000FF00                // CR_RX_PHASE_COMP_VAL_LG_RX1_PRI[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX1_PRI_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX0_PRI_ADDR WF_PHYRX_CTRL_CR_BF_SVD_8_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX0_PRI_MASK 0x000000FF                // CR_RX_PHASE_COMP_VAL_LG_RX0_PRI[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_8_CR_RX_PHASE_COMP_VAL_LG_RX0_PRI_SHFT 0

/* =====================================================================================

  ---CR_BF_SVD_9 (0x82000000 + 0x4C1C)---

    CR_RES_PHASE_COMP_VAL_TX0_PRI[7..0] - (RO) [CSD] iBF compensation value for TX0 primary segment
    CR_RES_PHASE_COMP_VAL_TX0_SEC[15..8] - (RO) [CSD] iBF compensation value for TX0 secondary segment
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_BF_SVD_9_CR_RES_PHASE_COMP_VAL_TX0_SEC_ADDR WF_PHYRX_CTRL_CR_BF_SVD_9_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_9_CR_RES_PHASE_COMP_VAL_TX0_SEC_MASK 0x0000FF00                // CR_RES_PHASE_COMP_VAL_TX0_SEC[15..8]
#define WF_PHYRX_CTRL_CR_BF_SVD_9_CR_RES_PHASE_COMP_VAL_TX0_SEC_SHFT 8
#define WF_PHYRX_CTRL_CR_BF_SVD_9_CR_RES_PHASE_COMP_VAL_TX0_PRI_ADDR WF_PHYRX_CTRL_CR_BF_SVD_9_ADDR
#define WF_PHYRX_CTRL_CR_BF_SVD_9_CR_RES_PHASE_COMP_VAL_TX0_PRI_MASK 0x000000FF                // CR_RES_PHASE_COMP_VAL_TX0_PRI[7..0]
#define WF_PHYRX_CTRL_CR_BF_SVD_9_CR_RES_PHASE_COMP_VAL_TX0_PRI_SHFT 0

/* =====================================================================================

  ---CR_MUTX_CONTROL_0 (0x82000000 + 0x4C20)---

    CR_TXBF_ERR_RPT_SEL[1..0]    - (RW) [DE] Select for more error reports.
    CR_MUTXBF_ERR_RPT_EN[2]      - (RW) [DE] Enable error report and interrupt when MUBF is not correctly applied.
    CR_ETXBF_ERR_RPT_EN[3]       - (RW) [DE] Enable error report and interrupt when eTxBF is not correctly applied.
    CR_ITXBF_ERR_RPT_EN[4]       - (RW) [DE] Enable error report and interrupt when iTxBF is not correctly applied.
    CR_ITXBF_APPLY_CHK_TO[5]     - (RW) [CSD] Check profile time-out value when applying iTxBF.
    CR_ITXBF_APPLY_CHK_ANT[6]    - (RW) [CSD] Check smart antenna config. when applying iTxBF.
    CR_ETXBF_APPLY_CHK_SE[7]     - (RW) [CSD] Check SE index when applying eTxBF.
    CR_ETXBF_APPLY_CHK_ANT[8]    - (RW) [CSD] Check smart antenna config. when applying eTxBF.
    CR_TXBF_RPT_FORCE_EN[9]      - (RW) [DE] Enable TxBF error report on every TxBF event.
    RESERVED10[22..10]           - (RO) Reserved bits
    CR_LG_APPLY_EPF_EN[23]       - (RW) Obsolete.
    CR_MUTXBF_EN[24]             - (RW) [DE] Enable Multi-user TxBF
    CR_ETXBF_EN[25]              - (RW) [DE] Enable eTxBF
    CR_ITXBF_EN[26]              - (RW) [DE] Enable iTxBF
    RESERVED27[27]               - (RO) Reserved bits
    CR_ETXBF_PL_EN[28]           - (RW) [CSD] Enable eTxBF power loading
    RESERVED29[30..29]           - (RO) Reserved bits
    CR_ITXBF_CBW160TO804020_ANT[31] - (RW) [DE] for iBF, if CBW160 but dbw 20/40/80, we divide anttena by 2

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_CBW160TO804020_ANT_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_CBW160TO804020_ANT_MASK 0x80000000                // CR_ITXBF_CBW160TO804020_ANT[31]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_CBW160TO804020_ANT_SHFT 31
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_PL_EN_ADDR    WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_PL_EN_MASK    0x10000000                // CR_ETXBF_PL_EN[28]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_PL_EN_SHFT    28
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_EN_ADDR       WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_EN_MASK       0x04000000                // CR_ITXBF_EN[26]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_EN_SHFT       26
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_EN_ADDR       WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_EN_MASK       0x02000000                // CR_ETXBF_EN[25]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_EN_SHFT       25
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_MUTXBF_EN_ADDR      WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_MUTXBF_EN_MASK      0x01000000                // CR_MUTXBF_EN[24]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_MUTXBF_EN_SHFT      24
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_LG_APPLY_EPF_EN_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_LG_APPLY_EPF_EN_MASK 0x00800000                // CR_LG_APPLY_EPF_EN[23]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_LG_APPLY_EPF_EN_SHFT 23
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_TXBF_RPT_FORCE_EN_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_TXBF_RPT_FORCE_EN_MASK 0x00000200                // CR_TXBF_RPT_FORCE_EN[9]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_TXBF_RPT_FORCE_EN_SHFT 9
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_APPLY_CHK_ANT_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_APPLY_CHK_ANT_MASK 0x00000100                // CR_ETXBF_APPLY_CHK_ANT[8]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_APPLY_CHK_ANT_SHFT 8
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_APPLY_CHK_SE_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_APPLY_CHK_SE_MASK 0x00000080                // CR_ETXBF_APPLY_CHK_SE[7]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_APPLY_CHK_SE_SHFT 7
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_APPLY_CHK_ANT_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_APPLY_CHK_ANT_MASK 0x00000040                // CR_ITXBF_APPLY_CHK_ANT[6]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_APPLY_CHK_ANT_SHFT 6
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_APPLY_CHK_TO_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_APPLY_CHK_TO_MASK 0x00000020                // CR_ITXBF_APPLY_CHK_TO[5]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_APPLY_CHK_TO_SHFT 5
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_ERR_RPT_EN_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_ERR_RPT_EN_MASK 0x00000010                // CR_ITXBF_ERR_RPT_EN[4]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ITXBF_ERR_RPT_EN_SHFT 4
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_ERR_RPT_EN_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_ERR_RPT_EN_MASK 0x00000008                // CR_ETXBF_ERR_RPT_EN[3]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_ETXBF_ERR_RPT_EN_SHFT 3
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_MUTXBF_ERR_RPT_EN_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_MUTXBF_ERR_RPT_EN_MASK 0x00000004                // CR_MUTXBF_ERR_RPT_EN[2]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_MUTXBF_ERR_RPT_EN_SHFT 2
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_TXBF_ERR_RPT_SEL_ADDR WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_TXBF_ERR_RPT_SEL_MASK 0x00000003                // CR_TXBF_ERR_RPT_SEL[1..0]
#define WF_PHYRX_CTRL_CR_MUTX_CONTROL_0_CR_TXBF_ERR_RPT_SEL_SHFT 0

/* =====================================================================================

  ---CR_MUTX_LQ_0 (0x82000000 + 0x4C24)---

    RESERVED0[27..0]             - (RO) Reserved bits
    CR_MUTX_LQ_SPEEDUP[29..28]   - (RW)  xxx
    RESERVED30[30]               - (RO) Reserved bits
    CR_MUTX_LQ_EN[31]            - (W1S) Enable Metric LQ calculation, write 1 and self-cleared after done.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_CR_MUTX_LQ_EN_ADDR          WF_PHYRX_CTRL_CR_MUTX_LQ_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_CR_MUTX_LQ_EN_MASK          0x80000000                // CR_MUTX_LQ_EN[31]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_CR_MUTX_LQ_EN_SHFT          31
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_CR_MUTX_LQ_SPEEDUP_ADDR     WF_PHYRX_CTRL_CR_MUTX_LQ_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_CR_MUTX_LQ_SPEEDUP_MASK     0x30000000                // CR_MUTX_LQ_SPEEDUP[29..28]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_0_CR_MUTX_LQ_SPEEDUP_SHFT     28

/* =====================================================================================

  ---CR_MUTX_LQ_1 (0x82000000 + 0x4C28)---

    CR_LQ_PF_ID_USER0[5..0]      - (RW) User-0 profile ID in PFMU. (0~63)
    CR_LQ_PF_ID_USER1[11..6]     - (RW) User-1 profile ID in PFMU. (0~63)
    CR_LQ_PF_ID_USER2[17..12]    - (RW) User-2 profile ID in PFMU. (0~63)
    CR_LQ_PF_ID_USER3[23..18]    - (RW) User-3 profile ID in PFMU. (0~63)
    CR_LQ_N_TXER[25..24]         - (RW) Metric nTxer.
                                     1~3: two ~ four antennas
    CR_LQ_N_USER[27..26]         - (RW) Metric nUser.
                                     0: single user
                                     1~3: two ~ four users
    CR_LQ_DBW[29..28]            - (RW) Metric DBW.
                                     0: BW20, 1: BW40, 2: BW80, 3: BW160
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_DBW_ADDR              WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_DBW_MASK              0x30000000                // CR_LQ_DBW[29..28]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_DBW_SHFT              28
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_N_USER_ADDR           WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_N_USER_MASK           0x0C000000                // CR_LQ_N_USER[27..26]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_N_USER_SHFT           26
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_N_TXER_ADDR           WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_N_TXER_MASK           0x03000000                // CR_LQ_N_TXER[25..24]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_N_TXER_SHFT           24
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER3_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER3_MASK      0x00FC0000                // CR_LQ_PF_ID_USER3[23..18]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER3_SHFT      18
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER2_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER2_MASK      0x0003F000                // CR_LQ_PF_ID_USER2[17..12]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER2_SHFT      12
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER1_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER1_MASK      0x00000FC0                // CR_LQ_PF_ID_USER1[11..6]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER1_SHFT      6
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER0_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_1_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER0_MASK      0x0000003F                // CR_LQ_PF_ID_USER0[5..0]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_1_CR_LQ_PF_ID_USER0_SHFT      0

/* =====================================================================================

  ---CR_MUTX_LQ_2 (0x82000000 + 0x4C2C)---

    CR_LQ_N_STS_USER0[1..0]      - (RW) User-0 nSTS, 0~1: one ~ two nSTS
    CR_LQ_N_STS_USER1[3..2]      - (RW) User-1 nSTS, 0~1: one ~ two nSTS
    CR_LQ_N_STS_USER2[5..4]      - (RW) User-2 nSTS, 0~1: one ~ two nSTS
    CR_LQ_N_STS_USER3[7..6]      - (RW) User-3 nSTS, 0~1: one ~ two nSTS
    CR_LQ_SE_IDX[12..8]          - (RW) Metric Spatial extension index, 0~27.
    CR_LQ_RU_SIZE[15..13]        - (RW) RU size;
                                     0: 26
                                     1: 52
                                     2: 106
                                     3: 242
                                     4: 484
                                     5: 996
    CR_LQ_PFD[19..16]            - (RW) Packet format;
                                     4: VHT
                                     8: HE SU
                                     9: HE EXT SU
                                     10: HE TRIG
                                     11: HE MU
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_PFD_ADDR              WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_PFD_MASK              0x000F0000                // CR_LQ_PFD[19..16]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_PFD_SHFT              16
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_RU_SIZE_ADDR          WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_RU_SIZE_MASK          0x0000E000                // CR_LQ_RU_SIZE[15..13]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_RU_SIZE_SHFT          13
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_SE_IDX_ADDR           WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_SE_IDX_MASK           0x00001F00                // CR_LQ_SE_IDX[12..8]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_SE_IDX_SHFT           8
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER3_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER3_MASK      0x000000C0                // CR_LQ_N_STS_USER3[7..6]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER3_SHFT      6
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER2_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER2_MASK      0x00000030                // CR_LQ_N_STS_USER2[5..4]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER2_SHFT      4
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER1_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER1_MASK      0x0000000C                // CR_LQ_N_STS_USER1[3..2]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER1_SHFT      2
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER0_ADDR      WF_PHYRX_CTRL_CR_MUTX_LQ_2_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER0_MASK      0x00000003                // CR_LQ_N_STS_USER0[1..0]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_2_CR_LQ_N_STS_USER0_SHFT      0

/* =====================================================================================

  ---CR_MUTX_LQ_3 (0x82000000 + 0x4C30)---

    CR_LQ_MCS_USER0[6..0]        - (RW) User0 MCS. RTL simulation only.
    CR_LQ_LDPC_USER0[7]          - (RW) User0 uses LDPC or BCC. RTL simulation only.
    CR_LQ_MCS_USER1[14..8]       - (RW) User1 MCS. RTL simulation only.
    CR_LQ_LDPC_USER1[15]         - (RW) User1 uses LDPC or BCC. RTL simulation only.
    CR_LQ_MCS_USER2[22..16]      - (RW) User2 MCS. RTL simulation only.
    CR_LQ_LDPC_USER2[23]         - (RW) User2 uses LDPC or BCC. RTL simulation only.
    CR_LQ_MCS_USER3[30..24]      - (RW) User3 MCS. RTL simulation only.
    CR_LQ_LDPC_USER3[31]         - (RW) User3 uses LDPC or BCC. RTL simulation only.

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER3_ADDR       WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER3_MASK       0x80000000                // CR_LQ_LDPC_USER3[31]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER3_SHFT       31
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER3_ADDR        WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER3_MASK        0x7F000000                // CR_LQ_MCS_USER3[30..24]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER3_SHFT        24
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER2_ADDR       WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER2_MASK       0x00800000                // CR_LQ_LDPC_USER2[23]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER2_SHFT       23
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER2_ADDR        WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER2_MASK        0x007F0000                // CR_LQ_MCS_USER2[22..16]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER2_SHFT        16
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER1_ADDR       WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER1_MASK       0x00008000                // CR_LQ_LDPC_USER1[15]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER1_SHFT       15
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER1_ADDR        WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER1_MASK        0x00007F00                // CR_LQ_MCS_USER1[14..8]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER1_SHFT        8
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER0_ADDR       WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER0_MASK       0x00000080                // CR_LQ_LDPC_USER0[7]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_LDPC_USER0_SHFT       7
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER0_ADDR        WF_PHYRX_CTRL_CR_MUTX_LQ_3_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER0_MASK        0x0000007F                // CR_LQ_MCS_USER0[6..0]
#define WF_PHYRX_CTRL_CR_MUTX_LQ_3_CR_LQ_MCS_USER0_SHFT        0

/* =====================================================================================

  ---CR_MUTX_PN (0x82000000 + 0x4C34)---

    CR_PN_MODE_SU[0]             - (RW) [CSD] PN mode for SU
                                     0: MAXTOTAL
                                     1: UNIFORM
    CR_PN_MODE_MU[1]             - (RW) [CSD] PN mode for MU
                                     0: MAXTOTAL
                                     1: UNIFORM
    RESERVED2[3..2]              - (RO) Reserved bits
    CR_MCS_BF_LB[7..4]           - (RW) [CSD] TX BF low-MCS on/off
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_MCS_BF_LB_ADDR             WF_PHYRX_CTRL_CR_MUTX_PN_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_MCS_BF_LB_MASK             0x000000F0                // CR_MCS_BF_LB[7..4]
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_MCS_BF_LB_SHFT             4
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_PN_MODE_MU_ADDR            WF_PHYRX_CTRL_CR_MUTX_PN_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_PN_MODE_MU_MASK            0x00000002                // CR_PN_MODE_MU[1]
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_PN_MODE_MU_SHFT            1
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_PN_MODE_SU_ADDR            WF_PHYRX_CTRL_CR_MUTX_PN_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_PN_MODE_SU_MASK            0x00000001                // CR_PN_MODE_SU[0]
#define WF_PHYRX_CTRL_CR_MUTX_PN_CR_PN_MODE_SU_SHFT            0

/* =====================================================================================

  ---CR_MUTX_SNR_OFFSET (0x82000000 + 0x4C38)---

    CR_MUTX_SNR_OFFSET[3..0]     - (RW) [CSD] MUTx SNR offset
    CR_MUTX_QD_NULL_COL0[4]      - (RW) [CSD] Null TxBF Qd matrix column 0
    CR_MUTX_QD_NULL_COL1[5]      - (RW) [CSD] Null TxBF Qd matrix column 1
    CR_MUTX_QD_NULL_COL2[6]      - (RW) [CSD] Null TxBF Qd matrix column 2
    CR_MUTX_QD_NULL_COL3[7]      - (RW) [CSD] Null TxBF Qd matrix column 3
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL3_ADDR WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL3_MASK 0x00000080                // CR_MUTX_QD_NULL_COL3[7]
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL3_SHFT 7
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL2_ADDR WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL2_MASK 0x00000040                // CR_MUTX_QD_NULL_COL2[6]
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL2_SHFT 6
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL1_ADDR WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL1_MASK 0x00000020                // CR_MUTX_QD_NULL_COL1[5]
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL1_SHFT 5
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL0_ADDR WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL0_MASK 0x00000010                // CR_MUTX_QD_NULL_COL0[4]
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_QD_NULL_COL0_SHFT 4
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_SNR_OFFSET_ADDR WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_SNR_OFFSET_MASK 0x0000000F                // CR_MUTX_SNR_OFFSET[3..0]
#define WF_PHYRX_CTRL_CR_MUTX_SNR_OFFSET_CR_MUTX_SNR_OFFSET_SHFT 0

/* =====================================================================================

  ---CR_MUTX_VMIX_BCC (0x82000000 + 0x4C3C)---

    CR_VMIX_EN_3STS_BCC[9..0]    - (RW) [CSD] Vmix enables for 3STS BCC packet.
    RESERVED10[15..10]           - (RO) Reserved bits
    CR_VMIX_EN_2STS_BCC[25..16]  - (RW) [CSD] Vmix enables for 2STS BCC packet.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_CR_VMIX_EN_2STS_BCC_ADDR WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_CR_VMIX_EN_2STS_BCC_MASK 0x03FF0000                // CR_VMIX_EN_2STS_BCC[25..16]
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_CR_VMIX_EN_2STS_BCC_SHFT 16
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_CR_VMIX_EN_3STS_BCC_ADDR WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_CR_VMIX_EN_3STS_BCC_MASK 0x000003FF                // CR_VMIX_EN_3STS_BCC[9..0]
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_BCC_CR_VMIX_EN_3STS_BCC_SHFT 0

/* =====================================================================================

  ---CR_MUTX_VMIX_LDPC (0x82000000 + 0x4C40)---

    CR_VMIX_EN_3STS_LDPC[9..0]   - (RW) [CSD] Vmix enables for 3STS LDPC packet.
    RESERVED10[15..10]           - (RO) Reserved bits
    CR_VMIX_EN_2STS_LDPC[25..16] - (RW) [CSD] Vmix enables for 2STS LDPC packet.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_CR_VMIX_EN_2STS_LDPC_ADDR WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_CR_VMIX_EN_2STS_LDPC_MASK 0x03FF0000                // CR_VMIX_EN_2STS_LDPC[25..16]
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_CR_VMIX_EN_2STS_LDPC_SHFT 16
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_CR_VMIX_EN_3STS_LDPC_ADDR WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_CR_VMIX_EN_3STS_LDPC_MASK 0x000003FF                // CR_VMIX_EN_3STS_LDPC[9..0]
#define WF_PHYRX_CTRL_CR_MUTX_VMIX_LDPC_CR_VMIX_EN_3STS_LDPC_SHFT 0

/* =====================================================================================

  ---CR_TX_PHASEALIGN_AND_PN (0x82000000 + 0x4CC4)---

    CR_TX_PHASER_EN[0]           - (RW) tx phase align master enable for SU
    CR_TX_PHASER_MU_EN[1]        - (RW) tx phase align enable for MU mode
    RESERVED2[3..2]              - (RO) Reserved bits
    CR_TX_PHASER_MCS_EN[13..4]   - (RW) tx phase align enable of each MCS mode
    RESERVED14[15..14]           - (RO) Reserved bits
    CR_PN_FORCE_1[16]            - (RW) 1ss PN force mode for debug
    CR_PN_FORCE_SQRT2[17]        - (RW) 2ss PN force mode for debug
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_PN_FORCE_SQRT2_ADDR WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_PN_FORCE_SQRT2_MASK 0x00020000                // CR_PN_FORCE_SQRT2[17]
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_PN_FORCE_SQRT2_SHFT 17
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_PN_FORCE_1_ADDR WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_PN_FORCE_1_MASK 0x00010000                // CR_PN_FORCE_1[16]
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_PN_FORCE_1_SHFT 16
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_MCS_EN_ADDR WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_MCS_EN_MASK 0x00003FF0                // CR_TX_PHASER_MCS_EN[13..4]
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_MCS_EN_SHFT 4
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_MU_EN_ADDR WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_MU_EN_MASK 0x00000002                // CR_TX_PHASER_MU_EN[1]
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_MU_EN_SHFT 1
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_EN_ADDR WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_EN_MASK 0x00000001                // CR_TX_PHASER_EN[0]
#define WF_PHYRX_CTRL_CR_TX_PHASEALIGN_AND_PN_CR_TX_PHASER_EN_SHFT 0

/* =====================================================================================

  ---CR_TX_PHASER_EN_3SS (0x82000000 + 0x4CC8)---

    CR_TX_PHASER_EN_1SS[0]       - (RW) [CSD] TX_PHASER_EN
    CR_TX_PHASER_EN_2SS[1]       - (RW) [CSD] TX_PHASER_EN
    CR_TX_PHASER_EN_3SS[2]       - (RW) [CSD] TX_PHASER_EN
    RESERVED3[31..3]             - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_3SS_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_3SS_MASK 0x00000004                // CR_TX_PHASER_EN_3SS[2]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_3SS_SHFT 2
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_2SS_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_2SS_MASK 0x00000002                // CR_TX_PHASER_EN_2SS[1]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_2SS_SHFT 1
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_1SS_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_1SS_MASK 0x00000001                // CR_TX_PHASER_EN_1SS[0]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_CR_TX_PHASER_EN_1SS_SHFT 0

/* =====================================================================================

  ---CR_TX_PHASER_EN_3SS_BCC (0x82000000 + 0x4CCC)---

    CR_TX_PHASER_EN_1SS_BCC[9..0] - (RW) [CSD] TX_PHASER_EN
    CR_TX_PHASER_EN_2SS_BCC[19..10] - (RW) [CSD] TX_PHASER_EN
    CR_TX_PHASER_EN_3SS_BCC[29..20] - (RW) [CSD] TX_PHASER_EN
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_3SS_BCC_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_3SS_BCC_MASK 0x3FF00000                // CR_TX_PHASER_EN_3SS_BCC[29..20]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_3SS_BCC_SHFT 20
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_2SS_BCC_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_2SS_BCC_MASK 0x000FFC00                // CR_TX_PHASER_EN_2SS_BCC[19..10]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_2SS_BCC_SHFT 10
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_1SS_BCC_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_1SS_BCC_MASK 0x000003FF                // CR_TX_PHASER_EN_1SS_BCC[9..0]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_BCC_CR_TX_PHASER_EN_1SS_BCC_SHFT 0

/* =====================================================================================

  ---CR_TX_PHASER_EN_3SS_LDPC (0x82000000 + 0x4CD0)---

    CR_TX_PHASER_EN_1SS_LDPC[9..0] - (RW) [CSD] TX_PHASER_EN
    CR_TX_PHASER_EN_2SS_LDPC[19..10] - (RW) [CSD] TX_PHASER_EN
    CR_TX_PHASER_EN_3SS_LDPC[29..20] - (RW) [CSD] TX_PHASER_EN
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_3SS_LDPC_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_3SS_LDPC_MASK 0x3FF00000                // CR_TX_PHASER_EN_3SS_LDPC[29..20]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_3SS_LDPC_SHFT 20
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_2SS_LDPC_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_2SS_LDPC_MASK 0x000FFC00                // CR_TX_PHASER_EN_2SS_LDPC[19..10]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_2SS_LDPC_SHFT 10
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_1SS_LDPC_ADDR WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_ADDR
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_1SS_LDPC_MASK 0x000003FF                // CR_TX_PHASER_EN_1SS_LDPC[9..0]
#define WF_PHYRX_CTRL_CR_TX_PHASER_EN_3SS_LDPC_CR_TX_PHASER_EN_1SS_LDPC_SHFT 0

/* =====================================================================================

  ---CR_ETXBF_PL_0 (0x82000000 + 0x4CD4)---

    CR_ETXBF_PL_MCS4_CN_TH[5..0] - (RW) [CSD] eTxBF power loading MCS4 CN threshold.
    CR_ETXBF_PL_MCS3_CN_TH[11..6] - (RW) [CSD] eTxBF power loading MCS3 CN threshold.
    CR_ETXBF_PL_MCS2_CN_TH[17..12] - (RW) [CSD] eTxBF power loading MCS2 CN threshold.
    CR_ETXBF_PL_MCS1_CN_TH[23..18] - (RW) [CSD] eTxBF power loading MCS1 CN threshold.
    CR_ETXBF_PL_MCS0_CN_TH[29..24] - (RW) [CSD] eTxBF power loading MCS0 CN threshold.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS0_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_0_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS0_CN_TH_MASK 0x3F000000                // CR_ETXBF_PL_MCS0_CN_TH[29..24]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS0_CN_TH_SHFT 24
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS1_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_0_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS1_CN_TH_MASK 0x00FC0000                // CR_ETXBF_PL_MCS1_CN_TH[23..18]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS1_CN_TH_SHFT 18
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS2_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_0_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS2_CN_TH_MASK 0x0003F000                // CR_ETXBF_PL_MCS2_CN_TH[17..12]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS2_CN_TH_SHFT 12
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS3_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_0_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS3_CN_TH_MASK 0x00000FC0                // CR_ETXBF_PL_MCS3_CN_TH[11..6]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS3_CN_TH_SHFT 6
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS4_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_0_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS4_CN_TH_MASK 0x0000003F                // CR_ETXBF_PL_MCS4_CN_TH[5..0]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_0_CR_ETXBF_PL_MCS4_CN_TH_SHFT 0

/* =====================================================================================

  ---CR_ETXBF_PL_1 (0x82000000 + 0x4CD8)---

    CR_ETXBF_PL_MCS9_CN_TH[5..0] - (RW) [CSD] eTxBF power loading MCS9 CN threshold.
    CR_ETXBF_PL_MCS8_CN_TH[11..6] - (RW) [CSD] eTxBF power loading MCS8 CN threshold.
    CR_ETXBF_PL_MCS7_CN_TH[17..12] - (RW) [CSD] eTxBF power loading MCS7 CN threshold.
    CR_ETXBF_PL_MCS6_CN_TH[23..18] - (RW) [CSD] eTxBF power loading MCS6 CN threshold.
    CR_ETXBF_PL_MCS5_CN_TH[29..24] - (RW) [CSD] eTxBF power loading MCS5 CN threshold.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS5_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_1_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS5_CN_TH_MASK 0x3F000000                // CR_ETXBF_PL_MCS5_CN_TH[29..24]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS5_CN_TH_SHFT 24
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS6_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_1_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS6_CN_TH_MASK 0x00FC0000                // CR_ETXBF_PL_MCS6_CN_TH[23..18]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS6_CN_TH_SHFT 18
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS7_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_1_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS7_CN_TH_MASK 0x0003F000                // CR_ETXBF_PL_MCS7_CN_TH[17..12]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS7_CN_TH_SHFT 12
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS8_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_1_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS8_CN_TH_MASK 0x00000FC0                // CR_ETXBF_PL_MCS8_CN_TH[11..6]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS8_CN_TH_SHFT 6
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS9_CN_TH_ADDR WF_PHYRX_CTRL_CR_ETXBF_PL_1_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS9_CN_TH_MASK 0x0000003F                // CR_ETXBF_PL_MCS9_CN_TH[5..0]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_1_CR_ETXBF_PL_MCS9_CN_TH_SHFT 0

/* =====================================================================================

  ---CR_ETXBF_PL_2 (0x82000000 + 0x4CDC)---

    CR_ETXBF_PL_CN10_G1[7..0]    - (RW) [CSD] eTxBF power loading g1 value when CN>=10
    CR_ETXBF_PL_CN10_G0[15..8]   - (RW) [CSD] eTxBF power loading g0 value when CN>=10
    CR_ETXBF_PL_CN0_G1[23..16]   - (RW) [CSD] eTxBF power loading g1 value when CN>=0
    CR_ETXBF_PL_CN0_G0[31..24]   - (RW) [CSD] eTxBF power loading g0 value when CN>=0

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN0_G0_ADDR    WF_PHYRX_CTRL_CR_ETXBF_PL_2_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN0_G0_MASK    0xFF000000                // CR_ETXBF_PL_CN0_G0[31..24]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN0_G0_SHFT    24
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN0_G1_ADDR    WF_PHYRX_CTRL_CR_ETXBF_PL_2_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN0_G1_MASK    0x00FF0000                // CR_ETXBF_PL_CN0_G1[23..16]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN0_G1_SHFT    16
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN10_G0_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_2_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN10_G0_MASK   0x0000FF00                // CR_ETXBF_PL_CN10_G0[15..8]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN10_G0_SHFT   8
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN10_G1_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_2_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN10_G1_MASK   0x000000FF                // CR_ETXBF_PL_CN10_G1[7..0]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_2_CR_ETXBF_PL_CN10_G1_SHFT   0

/* =====================================================================================

  ---CR_ETXBF_PL_3 (0x82000000 + 0x4CE0)---

    CR_ETXBF_PL_CN18_G1[7..0]    - (RW) [CSD] eTxBF power loading g1 value when CN>=18
    CR_ETXBF_PL_CN18_G0[15..8]   - (RW) [CSD] eTxBF power loading g0 value when CN>=18
    CR_ETXBF_PL_CN14_G1[23..16]  - (RW) [CSD] eTxBF power loading g1 value when CN>=14
    CR_ETXBF_PL_CN14_G0[31..24]  - (RW) [CSD] eTxBF power loading g0 value when CN>=14

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN14_G0_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_3_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN14_G0_MASK   0xFF000000                // CR_ETXBF_PL_CN14_G0[31..24]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN14_G0_SHFT   24
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN14_G1_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_3_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN14_G1_MASK   0x00FF0000                // CR_ETXBF_PL_CN14_G1[23..16]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN14_G1_SHFT   16
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN18_G0_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_3_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN18_G0_MASK   0x0000FF00                // CR_ETXBF_PL_CN18_G0[15..8]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN18_G0_SHFT   8
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN18_G1_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_3_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN18_G1_MASK   0x000000FF                // CR_ETXBF_PL_CN18_G1[7..0]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_3_CR_ETXBF_PL_CN18_G1_SHFT   0

/* =====================================================================================

  ---CR_ETXBF_PL_4 (0x82000000 + 0x4CE4)---

    CR_ETXBF_PL_CN26_G1[7..0]    - (RW) [CSD] eTxBF power loading g1 value when CN>=26
    CR_ETXBF_PL_CN26_G0[15..8]   - (RW) [CSD] eTxBF power loading g0 value when CN>=26
    CR_ETXBF_PL_CN22_G1[23..16]  - (RW) [CSD] eTxBF power loading g1 value when CN>=22
    CR_ETXBF_PL_CN22_G0[31..24]  - (RW) [CSD] eTxBF power loading g0 value when CN>=22

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN22_G0_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_4_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN22_G0_MASK   0xFF000000                // CR_ETXBF_PL_CN22_G0[31..24]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN22_G0_SHFT   24
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN22_G1_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_4_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN22_G1_MASK   0x00FF0000                // CR_ETXBF_PL_CN22_G1[23..16]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN22_G1_SHFT   16
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN26_G0_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_4_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN26_G0_MASK   0x0000FF00                // CR_ETXBF_PL_CN26_G0[15..8]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN26_G0_SHFT   8
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN26_G1_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_4_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN26_G1_MASK   0x000000FF                // CR_ETXBF_PL_CN26_G1[7..0]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_4_CR_ETXBF_PL_CN26_G1_SHFT   0

/* =====================================================================================

  ---CR_ETXBF_PL_5 (0x82000000 + 0x4CE8)---

    RESERVED0[15..0]             - (RO) Reserved bits
    CR_ETXBF_PL_CN30_G1[23..16]  - (RW) [CSD] eTxBF power loading g1 value when CN>=30
    CR_ETXBF_PL_CN30_G0[31..24]  - (RW) [CSD] eTxBF power loading g0 value when CN>=30

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_CR_ETXBF_PL_CN30_G0_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_5_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_CR_ETXBF_PL_CN30_G0_MASK   0xFF000000                // CR_ETXBF_PL_CN30_G0[31..24]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_CR_ETXBF_PL_CN30_G0_SHFT   24
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_CR_ETXBF_PL_CN30_G1_ADDR   WF_PHYRX_CTRL_CR_ETXBF_PL_5_ADDR
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_CR_ETXBF_PL_CN30_G1_MASK   0x00FF0000                // CR_ETXBF_PL_CN30_G1[23..16]
#define WF_PHYRX_CTRL_CR_ETXBF_PL_5_CR_ETXBF_PL_CN30_G1_SHFT   16

/* =====================================================================================

  ---CR_MUTX_MCS_TH_0 (0x82000000 + 0x4CEC)---

    RESERVED0[7..0]              - (RO) Reserved bits
    CR_MCS_TH_SHORT_3SS[11..8]   - (RW) [CSD] MCS threshold of SIG smoothing bit and BF bit for 3ss short channel
    CR_MCS_TH_LONG_3SS[15..12]   - (RW) [CSD] MCS threshold of SIG smoothing bit and BF bit for 3ss long channel
    CR_MCS_TH_SHORT_2SS[19..16]  - (RW) [CSD] MCS threshold of SIG smoothing bit and BF bit for 2ss short channel
    CR_MCS_TH_LONG_2SS[23..20]   - (RW) [CSD] MCS threshold of SIG smoothing bit and BF bit for 2ss long channel
    CR_MCS_TH_SHORT_1SS[27..24]  - (RW) [CSD] MCS threshold of SIG smoothing bit and BF bit for 1ss short channel
    CR_MCS_TH_LONG_1SS[31..28]   - (RW) [CSD] MCS threshold of SIG smoothing bit and BF bit for 1ss long channel

 =====================================================================================*/
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_1SS_ADDR WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_1SS_MASK 0xF0000000                // CR_MCS_TH_LONG_1SS[31..28]
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_1SS_SHFT 28
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_1SS_ADDR WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_1SS_MASK 0x0F000000                // CR_MCS_TH_SHORT_1SS[27..24]
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_1SS_SHFT 24
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_2SS_ADDR WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_2SS_MASK 0x00F00000                // CR_MCS_TH_LONG_2SS[23..20]
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_2SS_SHFT 20
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_2SS_ADDR WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_2SS_MASK 0x000F0000                // CR_MCS_TH_SHORT_2SS[19..16]
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_2SS_SHFT 16
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_3SS_ADDR WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_3SS_MASK 0x0000F000                // CR_MCS_TH_LONG_3SS[15..12]
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_LONG_3SS_SHFT 12
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_3SS_ADDR WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_ADDR
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_3SS_MASK 0x00000F00                // CR_MCS_TH_SHORT_3SS[11..8]
#define WF_PHYRX_CTRL_CR_MUTX_MCS_TH_0_CR_MCS_TH_SHORT_3SS_SHFT 8

#ifdef __cplusplus
}
#endif

#endif // __WF_PHYRX_CTRL_REGS_H__
